SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation - researchr publication

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Hyeyeong Lee, Joonhyung Kim, Jongsun Park. SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. In 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022. pages 5-6, IEEE, 2022. [doi]

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