Abstract is missing.
- High volume microprocessor test escapes, an analysis of defects our tests are missingWayne M. Needham, Cheryl Prunty, Yeoh Eng Hong. 25-34 [doi]
- Defect-oriented test quality assessment using fault sampling and simulationFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 35-42 [doi]
- Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experimentPhil Nigh, David P. Vallett, Atul Patel, Jason Wright. 43 [doi]
- Detection of CMOS address decoder open faults with March and pseudo random memory testsJan Otterstedt, Dirk Niggemeyer, T. W. Williams. 53-62 [doi]
- Consequences of port restrictions on testing two-port memoriesSaid Hamdioui, A. J. van de Goor. 63-72 [doi]
- A new framework for generating optimal March tests for memory arraysKamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty. 73 [doi]
- Delay test of chip I/Os using LSSD boundary scanPamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur. 83-90 [doi]
- Digital oscillation-test method for delay and stuck-at fault testing of digital circuitsKarim Arabi, Hassan Ihs, Christian Dufaza, Bozena Kaminska. 91-100 [doi]
- Designing for scan test of high performance embedded memoriesE. Kofi Vida-Torku, George Joos. 101 [doi]
- Maximizing handler thermal throughput with a rib-roughened test trayAndreas C. Pfahnl, John H. Lienhard V., Alexander H. Slocum. 109-113 [doi]
- Temperature control of a handler test interfaceAndreas C. Pfahnl, John H. Lienhard V., Alexander H. Slocum. 114-118 [doi]
- A test site thermal control system for at-speed manufacturing testingMark Malinoski, James Maveety, Steve Knostman, Tom Jones. 119 [doi]
- Testing embedded-core based system chipsYervant Zorian, Erik Jan Marinissen, Sujit Dey. 130 [doi]
- BETSY: synthesizing circuits for a specified BIST environmentZhe Zhao, Bahram Pouya, Nur A. Touba. 144-153 [doi]
- Test session oriented built-in self-testable data path synthesisHan Bin Kim, Takeshi Takahashi, Dong Sam Ha. 154-163 [doi]
- An algorithmic approach to optimizing fault coverage for BIST logic synthesisSrinivas Devadas, Kurt Keutzer. 164 [doi]
- Toward understanding Iddq-only failsAnne E. Gattiker, Wojciech Maly. 174-183 [doi]
- Analysis of pattern-dependent and timing-dependent failures in an experimental test chipJonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey. 184-193 [doi]
- CMOS IC reliability indicators and burn-in economicsAlan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell. 194-203 [doi]
- Defect detection with transient current testing and its potential for deep sub-micron CMOS ICsManoj Sachdev, Peter Janssen, Victor Zieren. 204 [doi]
- A distributed BIST technique for diagnosis of MCM interconnectionsRajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian. 214-221 [doi]
- Testing a multichip package for a consumer communications applicationAlex S. Biewenga, Math Muris, Rodger Schuttert, Urs Fawer. 222-227 [doi]
- Improved sensitivity for parallel test of substrate interconnectionsDavid C. Keezer, K. E. Newman, J. S. Davis. 228-233 [doi]
- A high throughput test methodology for MCM substratesBruce C. Kim, David C. Keezer, Abhijit Chatterjee. 234 [doi]
- Increasing the performance of arbitrary waveform generators using sigma-delta coding techniquesBenoit Dufort, Gordon W. Roberts. 241-248 [doi]
- When almost is good enough: a fresh look at DSP clock ratesEric Rosenfeld, Solomon Max. 249-253 [doi]
- Reduction of errors due to source and meter in the nonlinearity testLuke S. L. Hsieh. 254-257 [doi]
- Multi-output one-digitizer measurementS. Sasho, M. Shibata. 258 [doi]
- Cost of test reductionHervé Deshayes. 265-271 [doi]
- Fine pitch (45 micron) P4 probingToshinori Ishii, Hideaki Yoshida. 272-276 [doi]
- An introduction to area array probingFrederick L. Taber. 277-281 [doi]
- Integrated probe card/interface solutions for specific test applicationsJim Anderson. 282-283 [doi]
- A structured and scalable mechanism for test access to embedded reusable coresErik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters. 284-293 [doi]
- A structured test re-use methodology for core-based system chipsPrab Varma, Sandeep Bhatia. 294-302 [doi]
- Core test connectivity, communication, and controlLee Whetsel. 303-312 [doi]
- Modular logic built-in self-test for IP coresJanusz Rajski, Jerzy Tyszer. 313 [doi]
- A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuitsWen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu. 322-330 [doi]
- TAO: regular expression based high-level testability analysis and optimizationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. 331-340 [doi]
- A layout-based approach for ordering scan chain flip-flopsSamy Makar. 341-347 [doi]
- A new approach to scan chain reordering using physical design informationMokhtar Hirech, James Beausang, Xinli Gu. 348 [doi]
- Quad DCVS dynamic logic fault modeling and testingR. Dean Adams, Edmond S. Cooley, Patrick R. Hansen. 356-362 [doi]
- Switch-level bridging fault simulation in the presence of feedbacksPeter Dahlgren. 363-371 [doi]
- GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verificationSandip Kundu. 372 [doi]
- Digital bus faults measuring techniquesReuben Schrift. 382-387 [doi]
- Limited access testing: IEEE 1149.4-instrumentation and methodsJohn McDermid. 388-395 [doi]
- Generating interconnect models from prototype hardwareFrank W. Angelotti. 396-403 [doi]
- Built-in self-test of FPGA interconnectCharles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici. 404-411 [doi]
- Accumulator based deterministic BISTRainer Dorsch, Hans-Joachim Wunderlich. 412-421 [doi]
- A BIST scheme for the detection of path-delay faultsNilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik. 422 [doi]
- Microelectromechanical systems (MEMS) tutorialKaigham J. Gabriel. 432-441 [doi]
- A performance analysis system for MEMS using automated imaging methodsGlenn F. LaVigne, Sam L. Miller. 442 [doi]
- Scan chain design for test time reduction in core-based ICsJoep Aerts, Erik Jan Marinissen. 448-457 [doi]
- Test vector decompression via cyclical scan chains and its application to testing core-based designsAbhijit Jas, Nur A. Touba. 458-464 [doi]
- A novel test methodology for core-based system LSIs and a testing time minimization problemMakoto Sugihara, Hiroshi Date, Hiroto Yasuura. 465 [doi]
- Design and implementation of the G2 PowerPC 603e-embedded microprocessor coreCraig Hunter, Justin Gaither. 473-479 [doi]
- Diagnostic techniques for the UltraSPARC microprocessorsAnjali Kinra, Aswin Mehta, Neal Smith, Jackie Mitchell, Fred Valente. 480-486 [doi]
- Testability access of the high speed test features in the Alpha 21264 microprocessorDilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson. 487 [doi]
- Triggering and clocking architecture for mixed signal testNaveed Zaman, Antony Spilman. 496-499 [doi]
- A scalable architecture for VLSI testEd Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith. 500-506 [doi]
- The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solutionRobert Gage, Ben Brown. 507 [doi]
- Embedded self-testing checkers for low-cost arithmetic codesSteffen Tarnick, Albrecht P. Stroele. 514-523 [doi]
- On-line detection of logic errors due to crosstalk, delay, and transient faultsCecilia Metra, Michele Favalli, Bruno Riccò. 524-533 [doi]
- DfT and on-line test of high-performance data converters: a practical caseEduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas. 534 [doi]
- Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systemsA. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois. 541-550 [doi]
- Failure modes for stiction in surface-micromachined MEMSAbhijeet Kolpekwar, Ronald D. Blanton, David Woodilla. 551-556 [doi]
- MEMS fault model generation using CARAMELAbhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton. 557 [doi]
- Maximization of power dissipation under random excitation for burn-in testingKuo-Chan Huang, Chung-Len Lee, Jwu E. Chen. 567-576 [doi]
- High-coverage ATPG for datapath circuits with unimplemented blocksHyungwon Kim, John P. Hayes. 577-586 [doi]
- Implicit test generation for behavioral VHDL modelsFabrizio Ferrandi, Franco Fummi, Donatella Sciuto. 587 [doi]
- High quality, easy to use, on time ATE software Can it be done?Dan Proskauer. 597-605 [doi]
- Leveraging new standards in ATE softwareJohn Oonk. 606-611 [doi]
- Testing the design: the evolution of test simulationCraig Force, Tom Austin. 612 [doi]
- Extracting gate-level networks from simulation tablesPeter Wohl, John A. Waicukauski. 622-631 [doi]
- ATPG in practical and non-traditional applicationsBrion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs. 632-640 [doi]
- Test generation in VLSI circuits for crosstalk noiseWeiyu Chen, Sandeep K. Gupta, Melvin A. Breuer. 641 [doi]
- A comprehensive approach to the partial scan problem using implicit state enumerationPriyank Kalla, Maciej J. Ciesielski. 651-657 [doi]
- A novel combinational testability analysis by considering signal correlationShih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai. 658-667 [doi]
- DFT guidance through RTL test justification and propagation analysisYiorgos Makris, Alex Orailoglu. 668 [doi]
- Defect-oriented testing of mixed-signal ICs: some industrial experienceY. Xing. 678-687 [doi]
- A high speed and area efficient on-chip analog waveform extractorAra Hajjar, Gordon W. Roberts. 688-697 [doi]
- Stimulus generation for built-in self-test of charge-pump phase-locked loopsBenoît R. Veillette, Gordon W. Roberts. 698 [doi]
- Test methodology for a microprocessor with partial scanLeland L. Day, Paul A. Ganfield, Dennis M. Rickert, Fred J. Ziegler. 708-716 [doi]
- Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chipMary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott. 717-726 [doi]
- FakeFault: a silicon debug software tool for microprocessor embedded memory arraysYoung-Jun Kwon, Ben Mathew, Hong Hao. 727 [doi]
- Diagnosis and characterization of timing-related defects by time-dependent light emissionDaniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika. 733-739 [doi]
- Novel optical probing technique for flip chip packaged microprocessorsMario Paniccia, Travis M. Eiles, V. R. M. Rao, Wai Mun Yee. 740-747 [doi]
- On applying non-classical defect models to automated diagnosisJayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess. 748-757 [doi]
- A new path-oriented effect-cause methodology to diagnose delay failuresYuan-Chieh Hsu, Sandeep K. Gupta. 758 [doi]
- A fault injection environment for microprocessor-based boardsAlfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 768-773 [doi]
- Boundary scan BIST methodology for reconfigurable systemsChauchin Su, Shung-Won Jeng, Yue-Tsang Chen. 774-783 [doi]
- A lifecycle approach to design validation is it necessary? Is it feasible?Susana Stoica. 784-792 [doi]
- Can model-based and case-based expert systems operate together?Moshe Ben-Bassat, Israel Beniaminy, David Joseph. 793 [doi]
- Correlations between path delays and the accuracy of performance predictionLeendert M. Huisman. 801-808 [doi]
- High speed testing-have the laws of physics finally caught up with us?Jerry Katz. 809-813 [doi]
- Measuring jitter of high speed data channels using undersampling techniquesWajih Dalal, Daniel A. Rosenthal. 814-818 [doi]
- A method of serial data jitter analysis using one-shot time interval measurementsJan B. Wilstrup. 819 [doi]
- Alternative interface methods for testing high speed bidirectional signalsDavid C. Keezer, Q. Zhou. 824-830 [doi]
- AVM/sup TM/ a more usable way to execute vectors at double speedBob Hickling. 831-835 [doi]
- probe card-a solution for at-speed, high density, wafer probingRajiv Pandey, Dan Higgins. 836-842 [doi]
- Contactless gigahertz testingW. Mertin, Anton Leyk, Ulf Behnke, V. Wittpahl. 843 [doi]
- A highly testable and diagnosable fabrication process test chipDilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill. 853-861 [doi]
- Cache RAM inductive fault analysis with fab defect modelingT. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu. 862-871 [doi]
- Semiconductor manufacturing process monitoring using built-in self-test for embedded memoriesIvo Schanstra, Dharmajaya Lukita, A. J. van de Goor, Kees Veelenturf, Paul J. van Wijnen. 872 [doi]
- Estimation of defect-free IDDQ in submicron circuits using switch level simulationPeter C. Maxwell, Jeff Rearick. 882-889 [doi]
- Detecting resistive shorts for CMOS domino circuitsJonathan T.-Y. Chang, Edward J. McCluskey. 890-899 [doi]
- Defect level prediction for I_DDQ testingYukio Okuda, Isao Kubota, Masahiro Watanabe. 900 [doi]
- Versatile BIST: an integrated approach to on-line/off-line BISTRamesh Karri, Nilanjan Mukherjee. 910-917 [doi]
- R-CBIST: an effective RAM-based input vector monitoring concurrent BIST techniqueIoannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis. 918-925 [doi]
- On-line testing of scalable signal processing architectures using a software test methodChouki Aktouf, Ghassan Al Hayek, Chantal Robach. 926 [doi]
- A non-enumerative path delay fault simulator for sequential circuitsCarlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu. 934-943 [doi]
- Compact two-pattern test set generation for combinational and full scan circuitsIlker Hamzaoglu, Janak H. Patel. 944-953 [doi]
- Static test sequence compaction based on segment reordering and accelerated vector restorationSurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy. 954 [doi]
- Standard test interface language (STIL), extending the standardTony Taylor. 962-970 [doi]
- Defining ATPG rules checking in STILPeter Wohl, John A. Waicukauski. 971-979 [doi]
- Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standardBulent I. Dervisoglu, Mike Ricchetti, William Eklow. 980 [doi]
- Native mode functional test generation for processors with applications to self test and design validationJian Shen, Jacob A. Abraham. 990-999 [doi]
- A goal tree based high-level test planning system for DSP real number modelsMorris Lin, James R. Armstrong, F. Gail Gray. 1000-1009 [doi]
- Towards an automatic diagnosis for high-level design validationMaisaa Khalil, Yves Le Traon, Chantal Robach. 1010 [doi]
- Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental resultsClaude Thibeault, Luc Boisvert. 1019-1026 [doi]
- Process-tolerant test with energy consumption ratioBapiraju Vinnakota, Wanli Jiang, Dechang Sun. 1027-1036 [doi]
- Detection of bridging faults in logic resources of configurable FPGAs using I_DDQLan Zhao, D. M. H. Walker, Fabrizio Lombardi. 1037 [doi]
- Automated synthesis of large phase shifters for built-in self-testJanusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer. 1047-1056 [doi]
- Deterministic BIST with multiple scan chainsGundolf Kiefer, Hans-Joachim Wunderlich. 1057-1064 [doi]
- An almost full-scan BIST solution-higher fault coverage and shorter test application timeHuan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng. 1065 [doi]
- A diagnostic test generation procedure for synchronous sequential circuits based on test eliminationIrith Pomeranz, Sudhakar M. Reddy. 1074-1083 [doi]
- Probabilistic mixed-model fault diagnosisDavid B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto. 1084-1093 [doi]
- Modeling the unknown! Towards model-independent fault and error diagnosisVamsi Boppana, Masahiro Fujita. 1094 [doi]
- SRAM-based FPGA s: testing the LUT/RAM modulesMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 1102-1111 [doi]
- Built in self repair for embedded high density SRAMIlyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski. 1112-1119 [doi]
- How we test Siemens Embedded DRAM CoresRoderick McConnell, Udo Möller, Detlev Richter. 1120 [doi]
- Enough is enough alreadyWilliam R. Simpson. 1127 [doi]
- Test: when is enough enough?Bret A. Stewart. 1128 [doi]
- How much testing is enoughSusana Stoica. 1129 [doi]
- Spice up your life: simulate mixed-signal ICs!Keith Baker. 1131 [doi]
- Testing mixed signal SOCsMark Burns. 1132 [doi]
- When two worlds merge [test issues for system-level ICs]Ken Lanier. 1133 [doi]
- Accounting for the unexpected: fault diagnosis out of the ivory towerBrian Chess. 1135 [doi]
- ASIC jeopardy-diagnosing without a FABScott Davidson. 1136 [doi]
- Design for diagnostics views and experiencesVallluri R. Rao. 1137 [doi]
- IC diagnosis: preventing wars and war storiesJayashree Saxena. 1138 [doi]
- Scaling Deeper to Submicron: On-Line Testing to the RescueMichael Nicolaidis. 1139 [doi]
- Design for soft-error robustness to rescue deep submicron scalingMichael Nicolaidis. 1140 [doi]
- Learning to knit SOCs profitablyTodd E. Rockoff. 1142 [doi]
- SOC test: the devil is in the details of integration/implementationKamalesh N. Ruparel. 1143 [doi]
- System chip test: are we there yet?Prab Varma. 1144 [doi]
- On-chip versus off-chip test: an artificial dichotomyRobert C. Aitken. 1146 [doi]
- BIST vs. ATE for testing system-on-a-chipNeil Kelly. 1147 [doi]
- BIST vs. ATE: need a different vehicle?Stephen K. Sunter. 1148 [doi]
- BIST: required for embedded DRAMSatoru Tanoi. 1149 [doi]