Table of Contents

• Keynote AddressJon Fields. 3 [doi]
• Invited Keynote: Building Yield into Systems-on-Chips for Nanometer TechnologiesPhilippe Magarshack. 4 [doi]
• A Reconfigurable Shared Scan-in ArchitectureSamitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams. 9-14 [doi]
• Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan ArchitectureManish Sharma, Janak H. Patel, Jeff Rearick. 15-21 [doi]
• Transition Test Generation using Replicate-and-Reduce Transform for Scan-based DesignsMagdy S. Abadir, Juhong Zhu. 22-30 [doi]
• Use of Multiple IDDQ Test Metrics for Outlier IdentificationSagar S. Sabade, D. M. H. Walker. 31-38 [doi]
• Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICsBrady Benware, Robert Madge, Cam Lu, W. Robert Daasch. 39-46 [doi]
• Effectiveness of I-V Testing in Comparison to IDDq TestsThomas J. Vogels. 47-56 [doi]
• High Speed Ring Generators and Compactors of Test DataGrzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. 57-62 [doi]
• Built-In Reseeding for Serial BistAhmad A. Al-Yamani, Edward J. McCluskey. 63-68 [doi]
• Bist Reseeding with very few SeedsAhmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey. 69-76 [doi]
• Ultra Low Cost Analog BIST Using Spectral AnalysisMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 77-82 [doi]
• DSP-Based Statistical Self Test of On-Chip ConvertersHak-soo Yu, Sungbae Hwang, Jacob A. Abraham. 83-88 [doi]
• High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test CostSoumendu Bhattacharya, Abhijit Chatterjee. 89-100 [doi]
• Analysis and Design of Optimal Combinational CompactorsPeter Wohl, Leendert M. Huisman. 101-106 [doi]
• Application of Saluja-Karpovsky Compactors to Test Responses with Many UnknownsJanak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy. 107-112 [doi]
• Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and CompressionIsmet Bayraktaroglu, Alex Orailoglu. 113-120 [doi]
• Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential BusesKartik Mohanram, Nur A. Touba. 121-127 [doi]
• The Impact of NoC Reuse on the Testing of Core-based SystemsÉrika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin. 128-133 [doi]
• Automatic Configuration Generation for FPGA Interconnect TestingMehdi Baradaran Tahoori, Subhasish Mitra. 134-144 [doi]
• Threshold Voltage Mismatch (DeltaVT) Fault ModelingJosé Pineda de Gyvez, Rosa Rodríguez-Montañés. 145-150 [doi]
• Test Generation for Maximizing Ground Bounce Considering Circuit DelayYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer. 151-157 [doi]
• Testing SoC Interconnects for Signal Integrity Using Boundary ScanMohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani. 158-172 [doi]
• On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitIrith Pomeranz, Sudhakar M. Reddy. 173-178 [doi]
• An Efficient Test Relaxation Technique for Synchronous Sequential CircuitsAiman H. El-Maleh, Khaled Al-Utaibi. 179-185 [doi]
• Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test SetsNabil M. Abdulrazzaq, Sandeep K. Gupta. 186-196 [doi]
• 1149.4 Based On-Line Quiescent State Monitoring TechniqueChauchin Su, Chih-hu Wang, Wei-Juo Wang, I. S. Tseng. 197-202 [doi]
• Measurement of Phase and Frequency Variations in Radio-Frequency SignalMani Soma, Welela Haileselassie, Jessica Sherrid. 203-208 [doi]
• An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential CircuitsHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 209-218 [doi]
• Test Data Compression Using Dictionaries with Fixed-Length IndicesLei Li, Krishnendu Chakrabarty. 219-224 [doi]
• Deterministic Test Vector Decompression in Software Using Linear OperationsKedarnath J. Balakrishnan, Nur A. Touba. 225-231 [doi]
• Efficient Seed Utilization for Reseeding based CompressionErik H. Volkerink, Subhasish Mitra. 232-240 [doi]
• Detecting Intra-Word Faults in Word-Oriented MemoriesSaid Hamdioui, A. J. van de Goor, Mike Rodgers. 241-247 [doi]
• Test and Diagnosis of Word-Oriented Multiport MemoriesChih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu. 248-253 [doi]
• Generating Complete and Optimal March Tests for Linked Faults in MemoriesSultan M. Al-Harbi, Sandeep K. Gupta. 254-266 [doi]
• Energy-Efficient Logic BIST Based on State Correlation AnalysisXiaoding Chen, Michael S. Hsiao. 267-272 [doi]
• Power Constrained Test Scheduling with Dynamically Varied TAMDan Zhao, Shambhu J. Upadhyaya. 273-278 [doi]
• Development of Energy Consumption Ratio TestXiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota. 279-286 [doi]
• Design for Consecutive Transparency of Cores in System-on-a-ChipTomokazu Yoneda, Hideo Fujiwara. 287-292 [doi]
• An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC CoresMohsen Nahvi, André Ivanov. 293-298 [doi]
• Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCsVikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar. 299-312 [doi]
• Embedded Tutorial: Test Consideration for Nanometer Scale CMOS CircuitsKaushik Roy, T. M. Mak, Kwang-Ting Cheng. 313-318 [doi]
• Test Resource Partitioning and Optimization for SOC DesignsErik Larsson, Hideo Fujiwara. 319-324 [doi]
• SOC Test Scheduling Using Simulated AnnealingWei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang. 325-330 [doi]
• Layered Approach to Designing System Test InterfacesMan Wah Chiang, Zeljko Zilic. 331-338 [doi]
• Diagnosis of Delay Defects Using Statistical Timing ModelsAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou. 339-344 [doi]
• Improving Diagnostic Resolution of Delay Faults using Path Delay Fault ModelAnanta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger. 345-350 [doi]
• Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test GenerationXiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz. 351-358 [doi]
• BIST-Aided Scan Test - A New Method for Test Cost ReductionTakahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama. 359-364 [doi]
• Built-In TPG with Designed PhaseshiftsDimitri Kagaris. 365-370 [doi]
• A Test Interface for Built-In Test of Non-Isolated Scanned CoresIrith Pomeranz, Sudhakar M. Reddy, Yervant Zorian. 371-378 [doi]
• A Circuit Level Fault Model for Resistive Opens and BridgesZhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker. 379-384 [doi]
• Analyzing Crosstalk in the Presence of Weak Bridge DefectsShahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer. 385-392 [doi]
• Efficient Implication - Based Untestable Bridge Fault IdentifierManan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty. 393-402 [doi]
• Testable Design and Testing of Micro-Electro-Fluidic ArraysHans G. Kerkhoff, Mustafa Acar. 403-409 [doi]
• Fault Testing for Reversible CircuitsKetan N. Patel, John P. Hayes, Igor L. Markov. 410-416 [doi]
• Design for Self-Checking and Self-Timed DatapathJing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun. 417-430 [doi]