Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar. Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. In 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA. pages 299-312, IEEE Computer Society, 2003. [doi]
Abstract is missing.