Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar. Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. In 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA. pages 299-312, IEEE Computer Society, 2003. [doi]
@inproceedings{IyengarCKK03,
title = {Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs},
author = {Vikram Iyengar and Krishnendu Chakrabarty and Mark D. Krasniewski and Gopind N. Kumar},
year = {2003},
url = {http://csdl.computer.org/comp/proceedings/vts/2003/1924/00/19240299abs.htm},
tags = {optimization, architecture, design},
researchr = {https://researchr.org/publication/IyengarCKK03},
cites = {0},
citedby = {0},
pages = {299-312},
booktitle = {21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-1924-5},
}