Abstract is missing.
- Heterogeneous 3-d stacking, can we have the best of both (technology) worlds?Liam Madden. 1-2 [doi]
- Physical-aware system-level design for tiled hierarchical chip multiprocessorsJordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit. 3-10 [doi]
- Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systemsRobert Fischbach, Johann Knechtel, Jens Lienig. 11-16 [doi]
- Benchmarking for research in power delivery networks of three-dimensional integrated circuitsPei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi. 17-24 [doi]
- High performance and low power design techniques for ASIC and custom in nanometer technologiesDavid G. Chinnery. 25-32 [doi]
- Electromigration and its impact on physical design in future technologiesJens Lienig. 33-40 [doi]
- Data mining in design and test processes: basic principles and promisesLi-C. Wang. 41-42 [doi]
- SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variationYang Song, Hao Yu, Sai Manoj Pudukotai Dinakarrao, Guoyong Shi. 43-49 [doi]
- PushPull: short path padding for timing error resilient circuitsYu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho. 50-57 [doi]
- Dawn of computer-aided design: from graph-theory to place and routeAtsushi Takahashi. 58 [doi]
- Practicality on placement given by optimality of packingShigetoshi Nakatake. 59-60 [doi]
- On the way to practical tools for beyond die codesign and integrationHung-Ming Chen. 61 [doi]
- Coding the objects in place and route CADYoji Kajitani. 62-65 [doi]
- Circuit and PD challenges at the 14nm technology nodeJames Warnock. 66-67 [doi]
- Optical lithography extension with double patterningShigeki Nojima. 68 [doi]
- A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projectionRimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 69-76 [doi]
- Simultaneous OPC- and CMP-aware routing based on accurate closed-form modelingShao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang. 77-84 [doi]
- Planning for local net congestion in global routingHamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth. 85-92 [doi]
- Escape routing of mixed-pattern signals based on staggered-pin-array PCBsKan Wang, Huaxi Wang, Sheqin Dong. 93-100 [doi]
- Delay-driven layer assignment in global routing under multi-tier interconnect structureJianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto. 101-107 [doi]
- SRP: simultaneous routing and placement for congestion refinementXu He, Wing-Kai Chow, Evangeline F. Y. Young. 108-113 [doi]
- Case study for placement solutions in ispd11 and dac12 routability-driven placement contestsWen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li. 114-119 [doi]
- A compiler for scalable placement and routing of brain-like architecturesNarayan Srinivasa. 120-121 [doi]
- Physical design for debug: insurance policy for IC'sJohn Giacobbe. 122 [doi]
- A top-down synthesis methodology for flow-based microfluidic biochips considering valve-switching minimizationKai-Han Tseng, Sheng-Chi You, Jhe-Yu Liou, Tsung-Yi Ho. 123-129 [doi]
- Designing VeSFET-based ICs with CMOS-oriented EDA infrastructureXiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly. 130-136 [doi]
- ISPD 2013 expert designer/user session (eds)Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol. 137 [doi]
- Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reductionKenneth S. Stevens. 138 [doi]
- Network flow based datapath bit slicingHua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri. 139-146 [doi]
- FF-bond: multi-bit flip-flop bonding at placementChang-Cheng Tsai, Yiyu Shi, Guojie Luo, Iris Hui-Ru Jiang. 147-153 [doi]
- Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizesLogan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick. 154-161 [doi]
- Local merges for effective redundancy in clock networksRickard Ewetz, Cheng-Kok Koh. 162-167 [doi]
- An improved benchmark suite for the ISPD-2013 discrete cell sizing contestMuhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo. 168-170 [doi]
- TAU 2013 variation aware timing analysis contestDebjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita. 171-178 [doi]
- Opportunities and challenges for high performance microprocessor designs and design automationRuchir Puri. 179 [doi]
- To do or not to do hierarchical timing?Florentin Dartu, Qiuyang Wu. 180 [doi]
- Variability aware hierarchical implementation of big chipsVidyamani Parkhe. 181 [doi]
- Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closureShyam Ramji. 182 [doi]