Abstract is missing.
- Intelligent RAM (IRAM): The Industrial Setting, Applications and ArchitecturesDavid A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick. 2-7
- Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 MicroprocessorGabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan. 16-24
- Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSPBishop Brock, Warren A. Hunt Jr.. 31-36
- BIST-Based Fault Diagnosis in the Presence of Embedded MemoriesJacob Savir. 37-47
- Pseudo-Random Pattern Testing of Bridging FaultsNur A. Touba, Edward J. McCluskey. 54-60
- Novel Simulation of Deep-Submicron MOSFET CircuitsSerban Bruma, Ralph H. J. M. Otten. 62-67
- Time-Stamped Transition Density for the Estimation of Delay Dependent Switching ActivitiesHoon Choi, Seung Ho Hwang. 68-73
- Power Compiler: A Gate-Level Power Optimization and Synthesis SystemBenjamin Chen, Ivailo Nedelchev. 74-79
- Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction AccuracyMaria-Dana Tarlescu, Kevin B. Theobald, Guang R. Gao. 82-87
- Design Optimization for High-speed Per-address Two-level Branch PredictorsI-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge. 88-96
- PA-8000: A Case Study of Static and Dynamic Branch PredictionCarl Burch. 97-105
- Discrete Drive Selection for Continuous SizingRamsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy. 110-115
- Continuous Retiming: Algorithms and ApplicationsPeichen Pan. 116-121
- Comparison between nMos Pass Transistor logic style vs. CMOS Complementary CellsRakesh Mehrotra, Massoud Pedram, Xunwei Wu. 130-135
- Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power ElectronicsAndreas C. Cangellaris, W. Pinello, Albert E. Ruehli. 136-142
- Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC MicroprocessorAbhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning. 143-148
- Architectural Adaptation for Application-Specific Locality OptimizationXingbin Zhang, Ali Dasdan, Martin Schulz, Rajesh K. Gupta, Andrew A. Chien. 150-156
- A New Processor Architecture for Digital Signal Transport SystemsMinoru Inamori, Kenji Ishii, Akihiro Tsutsui, Kazuhiro Shirakawa, Hiroshi Nakada, Toshiaki Miyazaki. 157-162
- PROPHID: A Heterogeneous Multi-Processor Architecture for MultimediaJeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess. 164-169
- Enhanced Compression Techniques to Simplify Programm Decompression and ExecutionMauricio Breternitz Jr., Roger Smith. 170-176
- A Low Power Approach to Floating Point Adder DesignR. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili. 178-185
- Design and Implementation of Low-Power Digit-Serial MultipliersYun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi. 186-195
- On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares SolutionKhurram Muhammad, Kaushik Roy. 196-201
- An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC MicroprocessorsShervin Hojat, Paul Villarrubia. 206-210
- Post Layout Speed-up by Event EliminationHirendu Vaishnav, Chi-Keung Lee, Massoud Pedram. 211-216
- Clustering and Load Balancing for Buffered Clock Tree SynthesisAshih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi. 217-223
- CMOS Gate Delay Models for General RLC LoadingRavishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi. 224-229
- Design Methodology for the High-Performance G4 S/390Kenneth L. Shepard, Sean M. Carey, Daniel K. Beece, Robert F. Hatch, Gregory A. Northrop. 232-240
- A High-Frequency Custom CMOS S/390 MicroprocessorCharles F. Webb, John S. Liptay. 241-246
- High-Performance CMOS Circuit Techniques for the G-4 S/390 MicroprocessorJames D. Warnock, Leon J. Sigal, Brian W. Curran, Yuen H. Chan. 247-252
- A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex ExemplarRobert Castañeda, Xiaodong Zhang, James M. Hoover Jr.. 258-266
- Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based MultiprocessorHitoshi Oi, N. Ranganathan. 267-272
- An Approach to Network Caching for Multimedia ObjectsMichael Kozuch, Wayne Wolf, Andrew Wolfe. 273-278
- Development of a High Bandwidth Merged Logic/DRAM Multimedia ChipW. K. Luk, Y. Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi. 279-285
- TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive modelAkihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya. 288-294
- An Evaluation of Asynchronous and Synchronous Design for Superscalar ArchitecturesAndrew Davey, David Lloyd. 295-300
- Synthesizing Iterative Functions into Delay-Insensitive Tree CircuitsFu-Chiung Cheng. 301-306
- Asnchronous Wrapper for Heterogeneous SystemsDavid S. Bormann, Peter Y. K. Cheung. 307-314
- Design and Test: The Lost WorldWilliam H. Joyner Jr.. 328
- Equivalence Checking Using Abstract BDDsSomesh Jha, Yuan Lu, Marius Minea, Edmund M. Clarke. 332-337
- Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and SolutionsRajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 344-351
- Timed Binary Decision DiagramsZhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton. 352-357
- Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 360-365
- Nonenumerative Path Delay Fault Coverage Estimation with Optimal AlgorithmsDimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis. 366-371
- Properties of the Input Pattern Fault ModelRonald D. Blanton, John P. Hayes. 372-380
- A new Approach for Initialization Sequences Computation for Synchronous Sequential CircuitsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero. 381-386
- Real-Time Operating Systems for Embedded ComputingYanbing Li, Miodrag Potkonjak, Wayne Wolf. 388-392
- Allocation and Data Arrival Design of Hard Real-time SystemsDavid L. Rhodes, Wayne Wolf. 393-399
- Improving Design Turnaround Time via Two-Levels Hw/Sw Co-SimulationAlberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto. 400-405
- Power Constrained Design of Multiprocessor Interconnection NetworksChirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel. 408-416
- Memory Traffic and Data Cache Behavior of an MPEG-2 Software DecoderPeter Soderquist, Miriam Leeser. 417-422
- Asynchronous Transpose-Matrix ArchitecturesJosé A. Tierno, Prabhakar Kudva. 423-428
- A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural ProcessorWai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu. 429-434
- Formal Verification of the HAL S1 System Cache Coherence ProtocolAlan J. Hu, Masahiro Fujita, Chris Wilson. 438-444
- A Survey of Techniques for Formal Verification of Combinational CircuitsJawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli. 445-454
- Checking Formal Specifications under SimulationWilliam Canfield, E. Allen Emerson, Avijit Saha. 455-460
- Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic StructuresKarim Arabi, Bozena Kaminska. 462-467
- Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated CircuitsCheng-Ping Wang, Chin-Long Wey. 468-473
- A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal CircuitsJin Chen, Akhileswaran Ramachandran. 474-480
- On the Construction of Universal Series-Parallel Functions for Logic Module DesignFung Yu Young, D. F. Wong. 482-488
- A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAsJörn Stohmann, Erich Barke. 489-495
- Channel Segmentation Design for Symmentrical FPGAsWai-Kei Mak, D. F. Wong. 496-501
- Multi-Column Implementations for Cache AssociativityChenxi Zhang, Xiaodong Zhang, Yong Yan. 504-509
- Design and Performance Evaluation of a Cache Assist to implement Selective CachingLizy Kurian John, Akila Subramanian. 510-518
- On Effective Data Supply For Multi-Issue ProcessorsJude A. Rivers, Edward S. Tam, Edward S. Davidson. 519-528
- Practical Issues of Interconnect Analysis in Deep Submicron Integrated CircuitsKenneth L. Shepard. 532-541
- First Test Results of System Level Fault Tolerant Design Validation Through Laser Fault InjectionWilfrido A. Moreno, Fernando J. Falquez, John R. Samson Jr., Thomas Smith. 544-548
- Integrated Diagnostics for Embedded Memory Built-in Self Test on Power PC:::TM::: DevicesCraig Hunter. 549-554
- A TSC Evaluation Function for Combinational CircuitsCristiana Bolchini, Donatella Sciuto, Fabio Salice. 555-560
- An Architectural Power Optimization Case Study using High-level SynthesisChih-Tung Chen, Kayhan Küçükçakar. 562-570
- High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech EncoderRusell E. Henning, Chaitali Chakrabarti. 571-576
- Fast Cache Access with Full-Map Block DirectoryJih-Kwon Peir, Windsor W. Hsu. 578-586
- A Data Alignment Technique for Improving Cache PerformancePreeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau. 587-592
- Instruction Prefetching Using Branch Prediction InformationI-Cheng K. Chen, Chih-Chieh Lee, Trevor N. Mudge. 593-601
- An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI CircuitsX. Tan, J. Tong, P. Tan, Nohpill Park, Fabrizio Lombardi. 608-613
- Partitioning Under Timing and Area ConstraintsGregory Tumbush, Dinesh Bhatia. 614-620
- A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell PlacementJohn A. Chandy, Prithviraj Banerjee. 621-627
- Crosstalk-Constrained Maze Routing Based on Lagrangian RelaxationHai Zhou, D. F. Wong. 628-633
- High Level Test Synthesis Across the Boundary of Behavioral and Structural DomainsKowen Lai, Christos A. Papachristou, Mikhail Baklashov. 636-641
- Power Driven Partial ScanJing-Yang Jou, Ming-Chang Nien. 642-647
- Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced ScanRamesh C. Tekumalla, Premachandran R. Menon. 648-653
- Application of a Testing Framework to VHDL Descriptions at Different Abstraction LevelsM. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto. 654-658
- Practical Advances in Asynchronous DesignErik Brunvand, Steven M. Nowick, Kenneth Y. Yun. 662-668
- Benchmarking and Analysis of Architectures for CAD ApplicationsAmit Mehrotra, Shaz Qadeer, Rajeev K. Ranjan, Randy H. Katz. 670-675
- Fast Low-Energy VLSI Binary AdditionKeshab K. Parhi. 676-684
- A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock SchemeHiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano. 685-689
- Parallel-Array Implementations of a Non-Restoring Square Root AlgorithmYamin Li, Wanming Chu. 690-695
- Optimizing CMOS Implementations of the C-elementMaitham Shams, Jo C. Ebergen, Mohamed I. Elmasry. 700-705
- A Double-Latched Asynchronous PipelineRakefet Kol, Ran Ginosar. 706-712
- A Pulse-To-Static Conversion Latch with a Self-Timed Control CircuitWei Hwang, Rajiv V. Joshi, Walter H. Henkels. 712-717
- Fast Generation of Statistically-based Worst-Case Modeling of On-Chip InterconnectNorman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh. 720-725
- A Repeater Optimization Methodology for Deep Sub-Micron, High Performance ProcessorsDavid Li, Andrew Pua, Pranjal Srivastava, Uming Ko. 726-731
- Divide & Conquer: A Strategy for Synthesis of Low Power Finite State MachinesAurobindo Dasgupta, Shantanu Ganguly. 740-745
- Estimation of Maximum Power for Sequential Circuits Considering Spurious TransitionsChuan-Yu Wang, Kaushik Roy. 746-751
- Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling AlgorithmsSriram Govindarajan, Ranga Vemuri. 752-757