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TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model

Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya. TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. In ICCD. pages 288-294, 1997.

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