Chang Wu, Jundong Xie, Kexin Wang. Highly Efficient Modulo Loop Pipeline For High Level Synthesis. In Fan Ye, Ting-Ao Tang, editors, 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021. pages 1-4, IEEE, 2021. [doi]
Abstract is missing.