Table of Contents

• Compiler Support for Structured DataSaman P. Amarasinghe. 1-2 [doi]
• DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLSLinus Y. Wong, Jialiang Zhang, Jing Jane Li. 3-13 [doi]
• FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAsLinfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang 0012. 15-25 [doi]
• Eliminating Excessive Dynamism of Dataflow Circuits Using Model CheckingJiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic. 27-37 [doi]
• Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow CircuitsAyatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne. 39-45 [doi]
• OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory PlatformRakin Muhammad Shadab, Yu Zou, Sanjay Gandham, Mingjie Lin. 47 [doi]
• Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA PlatformsKaveh Aasaraai, Emanuele Cesena, Rahul Maganti, Nicolas Stalder, Javier Varela, Kevin Bowers. 47 [doi]
• AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer ArchitectureHyeong-Ju Kang. 48 [doi]
• Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space StationTim Oberschulte, Jakob Marten, Holger Blume. 48 [doi]
• Nimblock: Scheduling for Fine-grained FPGA Sharing through VirtualizationMeghna Mandava, Deming Chen. 49 [doi]
• Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural NetworksRuiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu, Kun Wang. 49 [doi]
• An Efficient High-Speed FFT ImplementationRoss-Martin. 50 [doi]
• HMLib: Efficient Data Transfer for HLS Using Host MemoryMichael Lo, Young Kyu Choi, Weikang Qiao, Mau-Chung Frank Chang, Jason Cong. 50 [doi]
• A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power ConvertersZhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong, Tao Wei. 51 [doi]
• Weave: Abstraction for Accelerator Integration of Generated ModulesTuo Dai, Bizhao Shi, Guojie Luo. 51 [doi]
• A Fractal Astronomical Correlator Based on FPGA Cluster with ScalabilityLin Shu, Long Xiao, Yafang Song, Qiuxiang Fan, Guitian Fang, Jie Hao. 52 [doi]
• Power Side-channel Countermeasures for ARX Ciphers using High-level SynthesisSaya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi. 52 [doi]
• Single-Batch CNN Training using Block Minifloats on FPGAsChuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong. 53 [doi]
• A Study of Early Aggregation in Database Query Processing on FPGAsMehdi Moghaddamfar, Norman May, Christian Färber, Wolfgang Lehner, Akash Kumar 0001. 55-65 [doi]
• FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph ConstructionChaoqiang Liu, Haifeng Liu, Long Zheng 0003, Yu Huang 0013, Xiangyu Ye, Xiaofei Liao, Hai Jin 0001. 67-77 [doi]
• ACTS: A Near-Memory FPGA Graph Processing FrameworkWole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron. 79-89 [doi]
• Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection SimulationNick Brown. 91-97 [doi]
• Regularity Matters: Designing Practical FPGA Switch-BlocksStefan Nikolic, Paolo Ienne. 99-109 [doi]
• Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital ConvertersColin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. 111-122 [doi]
• Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoCAndrew Elbert Wilson, Nathan Baker, Ethan Campbell, Jackson Sahleen, Michael J. Wirthlin. 123-133 [doi]
• FPGA Technology Mapping with Adaptive Gate DecompositionLongfei Fan, Chang Wu. 135-140 [doi]
• FPGA Mux Usage and Routability Estimates without Explicit RoutingJonathan W. Greene. 141-147 [doi]
• Open-source and FPGAs: Hardware, Software, Both or None?Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon. 149 [doi]
• FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoCJaideep Dastidar. 151 [doi]
• CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP ArchitectureJinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou 0001. 153-164 [doi]
• Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image ProcessingAlireza Khataei, Gaurav Singh, Kia Bazargan. 165-175 [doi]
• Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize SearchLei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang. 177-183 [doi]
• hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGAXuan Wang, Lei Gong, Jing Cao, Wenqi Lou, Weiya Wang, Chao Wang, Xuehai Zhou. 185-196 [doi]
• CSAIL2019 Crypto-Puzzle Solver ArchitectureSergey Gribok, Bogdan Pasca 0001, Martin Langhammer. 197-207 [doi]
• ENCORE: Efficient Architecture Verification Framework with FPGA AccelerationKan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao. 209-219 [doi]
• BOBBER A Prototyping Platform for Batteryless Intermittent AcceleratorsVishak Narayanan, Rohit Sahu, Jidong Sun, Henry Duwe. 221-228 [doi]
• Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication SchemeMingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu 0001. 229 [doi]
• Adapting Skip Connections for Resource-Efficient FPGA InferenceOlivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Nojan Sheybani, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner. 229 [doi]
• Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN IsolationBharat Sukhwani, Mohit Kapur, Alda Ohmacht, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes, Sameh W. Asaad. 230 [doi]
• LAWS: Large-Scale Accelerated Wave Simulations on FPGAsDimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy Kurian John, Andreas Gerstlauer. 230 [doi]
• Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA RoutingShashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic. 231 [doi]
• Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing ProblemsAndrew David Gunter, Steven Wilton. 231 [doi]
• An FPGA-Based Weightless Neural Network for Edge Network Intrusion DetectionZachary Susskind, Aman Arora, Alan T. L. Bacellar, Diego Leonel Cadette Dutra, Igor D. S. Miranda, Maurício Breternitz, Priscila M. V. Lima, Felipe M. G. França, Lizy K. John. 232 [doi]
• A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based AcceleratorsYongzheng Chen, Gang Wu 0007. 232 [doi]
• Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop AcceleratorsEmanuele Del Sozzo, Davide Conficconi, Marco D. Santambrogio, Kentaro Sano. 233 [doi]
• FPGA Acceleration for Successive Interference Cancellation in Severe Multipath Acoustic Communication ChannelsJinfeng Li, Yahong Rosa Zheng. 233 [doi]
• FreezeTime: Towards System Emulation through Architectural VirtualizationSergiu Mosanu, Joshua Fixelle, Kevin Skadron, Mircea Stan. 234 [doi]
• A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via on-chip Dynamic Tree ManagementYuan Meng, Rajgopal Kannan, Viktor K. Prasanna. 235-245 [doi]
• Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient SolverLinghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong. 247-258 [doi]
• Accelerating Sparse MTTKRP for Tensor Decomposition on FPGASasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna. 259-269 [doi]