- Keisuke Sugiura, Hiroki Matsutani. FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features. TRETS, 18(2), June 2025.
- Giovanni Brignone, Roberto Bosio, Fabrizio Ottati, Claudio Sansoè, Luciano Lavagno. SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators. TRETS, 18(2), June 2025.
- Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong. FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network. TRETS, 18(2), June 2025.
- Gaurav Singh, Kia Bazargan. Compressing Neural Networks using Learnable 1D Non-Linear Functions. TRETS, 18(2), June 2025.
- Yaswanth Tavva, Rohan Juneja, Trevor E. Carlson, Li-Shiuan Peh. CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs. TRETS, 18(2), June 2025.
- Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase. A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks. TRETS, 18(1), 2025.
- Chenfeng Zhao, Clayton J. Faber, Roger D. Chamberlain, Xuan Zhang 0001. HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures. TRETS, 18(1), 2025.
- Mingqian Sun, Guangwei Xie, Fan Zhang 0044, Wei Guo, Xitian Fan, Li Chen, Jiayu Du. FPGA-Based Large-Scale Sorting with Optimized Bandwidth Utilization. TRETS, 18(2), June 2025.
- Muhammed Kawser Ahmed, Maximillian Kealoha Panoff, Joel Mandebi Mbongue, Sujan Kumar Saha, Erman Nghonda Tchinda, Peter Esenju Mbua, Christophe Bobda. Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy. TRETS, 18(2), June 2025.
- Ahmed F. AbouElhamayed, Angela Cui, Javier Fernández-Marqués, Nicholas D. Lane, Mohamed S. Abdelfattah. PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration. TRETS, 18(1), 2025.