Abstract is missing.
- The P4->NetFPGA Workflow for Line-Rate Packet ProcessingStephen Ibanez, Gordon J. Brebner, Nick McKeown, Noa Zilberman. 1-9 [doi]
- Visual System Integrator: Invited TutorialSandeep Dutta, Adnan Yunus, Artem Marisov, Matt Menezes, Somayeh Rahimipour. 10-13 [doi]
- Build Your Own Domain-specific Solutions with RapidWright: Invited TutorialChris Lavin, Alireza Kaviani. 14-22 [doi]
- Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAsYifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma 0003, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer. 23-32 [doi]
- REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAsCaiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang 0001. 33-42 [doi]
- Reconfigurable Convolutional Kernels for Neural Networks on FPGAsMartin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf. 43-52 [doi]
- F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional ComputingSahand Salamat, Mohsen Imani, Behnam Khaleghi, Tajana Rosing. 53-62 [doi]
- Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced SparsityShijie Cao, Chen Zhang, Zhuliang Yao, Wencong Xiao, Lanshun Nie, De-chen Zhan, Yunxin Liu, Ming Wu, Lintao Zhang. 63-72 [doi]
- Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAsYao Chen, Jiong He, Xiaofan Zhang, Cong Hao, Deming Chen. 73-82 [doi]
- Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP)Kees A. Vissers. 83 [doi]
- TM ArchitectureBrian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer. 84-93 [doi]
- Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAsAndrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz. 94-103 [doi]
- LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image StabilizationZhe Chen, Hugh T. Blair, Jason Cong. 104-109 [doi]
- On-chip FPGA Debug Instrumentation for Machine Learning ApplicationsDaniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton. 110-115 [doi]
- Scheduling Data in Neural Network ApplicationsThaddeus Koehn, Peter Athanas. 116 [doi]
- Base64 Encoding on OpenCL FPGA PlatformZheming Jin, Hal Finkel. 116 [doi]
- Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA EmulationTom J. Mannos, Brian Dziki, Moslema Sharif. 116 [doi]
- Scalable High Performance SDN Switch Architecture on FPGA for Core NetworksSasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual. 117 [doi]
- SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured Sparsity in Binary Neural NetworkXin He, Liu Ke, Xuan Zhang. 117-118 [doi]
- A Deep-Reinforcement-Learning-Based Scheduler for High-Level SynthesisHongzheng Chen, Minghua Shen. 117 [doi]
- Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA SystemJunzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang. 117 [doi]
- A Deep Learning Inference Accelerator Based on Model Compression on FPGALu Jing, Jun Liu, FuHai Yu. 118 [doi]
- Sparse Winograd Convolutional Neural Networks on Small-scale Systolic ArraysFeng Shi, Haochen Li, Yuhe Gao, Benjamin Kuschner, Song Chun Zhu. 118 [doi]
- HSC-FPGARamtin Zand, Ronald F. DeMara. 118-119 [doi]
- Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AIEriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu. 119 [doi]
- Parrot: A More Effective Parallel Routing Approach to FPGAsMinghua Shen, Nong Xiao. 119 [doi]
- A Reconfigurable Accelerator for Sparse Convolutional Neural NetworksWeijie You, Chang Wu. 119 [doi]
- A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts InferenceTianqi Gao, Rob A. Rutenbar. 120 [doi]
- Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory ManagmentXuechao Wei, Yun Liang 0001, Peng Zhang, Cody Hao Yu, Jason Cong. 120 [doi]
- Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product QuantizationJialiang Zhang, Jing Li. 120 [doi]
- Transistor-Level Optimization Methodology for GRM FPGA Interconnect CircuitsZhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai. 121 [doi]
- Highly Efficient Sparse Neural Network Computing: Hardware and Software SolutionsYanjie Gu, Jian Yu, Tieli Sun, Chen Pan, Zhenhao Feng, Liewei Xu, Chang Wu. 121 [doi]
- FPGA-based Distributed Edge Training of SVMJyotikrishna Dass, Yashwardhan Narawane, Rabi N. Mahapatra, Vivek Sarin. 121 [doi]
- Multi-Commodity Flow-Based Spreading in a Commercial Analytic PlacerNima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu. 122-131 [doi]
- Simultaneous Placement and Clock Tree Construction for Modern FPGAsWuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan. 132-141 [doi]
- EASY: Efficient Arbiter SYnthesis from Multi-threaded CodeJianyi Cheng, Shane T. Fleming, Yu-Ting Chen, Jason Helge Anderson, George A. Constantinides. 142-151 [doi]
- Substream-Centric Maximum Matchings on FPGAMaciej Besta, Marc Fischer, Tal Ben-Nun, Johannes de Fine Licht, Torsten Hoefler. 152-161 [doi]
- Speculative Dataflow CircuitsLana Josipovic, Andrea Guerrieri, Paolo Ienne. 162-171 [doi]
- Constructing Concurrent Data Structures on FPGA with ChannelsHui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei. 172-177 [doi]
- Rapid Cycle-Accurate Simulator for High-Level SynthesisYuze Chi, Young Kyu Choi, Jason Cong, Jie Wang. 178-183 [doi]
- PAI-FCNN: FPGA Based CNN Inference SystemLansong Diao, Zhao Jiang, Hao Liang, Chang'an Ye, Kai Chen 0008, Li Ding, Shunli Dou, Meng Sun, Lixue Xia, Jiansong Zhang, Wei Lin. 184 [doi]
- MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA PlacementYun Zhou, Dries Vercruyce, Dirk Stroobandt. 184 [doi]
- JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-coresKatie Lim, Jonathan Balkind, David Wentzlaff. 184 [doi]
- A Fine-Grained Sparse Accelerator for Multi-Precision DNNShulin Zeng, Yujun Lin, Shuang Liang, Junlong Kang, Dongliang Xie, Yi Shan, Song Han, Yu Wang, Huazhong Yang. 185 [doi]
- SwitchAgg: A Further Step Towards In-Network ComputationFan Yang, Zhan Wang, Xiaoxiao Ma, Guojun Yuan, Xuejun An. 185 [doi]
- A PYNQ-compliant Online Platform for Zynq-based DNN DevelopersChen Chen, Jun Xia, Wenmin Yang, Kang Li, ZhiLei Chai. 185 [doi]
- Building FPGA State Machines from Sequential CodeCarl-Johannes Johnsen, Kenneth Skovhede. 186 [doi]
- Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration PlatformDario Korolija, Mirjana Stojilovic. 186 [doi]
- An FPGA-based Fine Tuning Accelerator for a Sparse CNNHiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato. 186 [doi]
- Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAsLiqiang Lu, Yun Liang 0001, Ruirui Huang, Wei Lin, Xiaoyuan Cui, Jiansong Zhang. 187 [doi]
- Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space ComplexityJiafeng Xie, Chiou-Yng Lee. 187 [doi]
- Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level SynthesisJie Liu, Jason Cong. 187 [doi]
- DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN AcceleratorsYu Xing, Shuang Liang, Lingzhi Sui, Zhen Zhang, Jiantao Qiu, Xijie Jia, Xin Liu, Yushun Wang, Yi Shan, Yu Wang. 187-188 [doi]
- On Feasibility of FPGAs Without Dedicated Programmable Interconnect StructureAnastasiia Kucherenko, Stefan Nikolic, Paolo Ienne. 188 [doi]
- Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise FingerprintingYazhu Lan, Qingli Guo, Guohe Zhang, Yuanchao Xu, Kent W. Nixon, Hai Helen Li, Yiran Chen. 188-189 [doi]
- A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA PlatformsLiang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang. 188 [doi]
- FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural NetworksZhucheng Tang, Guojie Luo, Ming Jiang 0001. 189 [doi]
- Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data ReuseJuan Escobedo, Mingjie Lin. 189-190 [doi]
- Compressed CNN Training with FPGA-based AcceleratorKaiyuan Guo, Shuang Liang, Jincheng Yu, Xuefei Ning, Wenshuo Li, Yu Wang, Huazhong Yang. 189 [doi]
- PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAsKonstantinos Maragos, George Lentaris, Dimitrios Soudris, Vasilis F. Pavlidis. 190 [doi]
- Software Hardware Co-Optimized BFS on FPGAsZachary Sherer, Eric Finnerty, Yan Luo, Hang Liu. 190 [doi]
- Compute-Efficient Neural-Network AccelerationEphrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho, John Thendean. 191-200 [doi]
- FPGAs in Supercomputers: Opportunity or Folly?Deming Chen. 201 [doi]
- Fractal Synthesis: Invited TutorialMartin Langhammer, Gregg Baeckler, Sergey Gribok. 202-211 [doi]
- TM ACAP ArchitectureIan Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel. 212-221 [doi]
- HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOsTushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre. 222-231 [doi]
- The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAsDaniel Rozhko, Paul Chow. 232-241 [doi]
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable ComputingYi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang. 242-251 [doi]
- AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision AlgorithmsSajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau. 252-261 [doi]
- A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data CenterNariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow. 262-271 [doi]
- Impact of Soft Errors on Large-Scale FPGA Cloud ComputingAndrew M. Keller, Michael J. Wirthlin. 272-281 [doi]
- Breaking the Trust Dependence on Third Party Processes for Reconfigurable Secure HardwareAimee Coughlin, Greg Cusack, Jack Wampler, Eric Keller, Eric Wustrow. 282-291 [doi]
- Characterization of Long Wire Data Leakage in Deep Submicron FPGAsGeorge Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel Holcomb. 292-297 [doi]
- Temporal Thermal Covert Channels in Cloud FPGAsShanquan Tian, Jakub Szefer. 298-303 [doi]
- How to Accelerate FPGA Application in an Asynchronous Way?Anping He, Jinlin Zhang, Lvying Yu, Pengfei Li, Lian Li. 304 [doi]
- Nuclear Reactor Simulations on OpenCL FPGA PlatformZheming Jin, Hal Finkel. 304 [doi]
- Storage Mirroring for Bare-Metal Systems on FPGA DevicesDan Cristian Turicu, Octavian Cret, Lucia Vacariu. 304-305 [doi]
- XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AIWeiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Lei Yang 0018, Yiyu Shi, Jingtong Hu. 305 [doi]
- Fast Inference of Deep Neural Networks for Real-time Particle Physics ApplicationsJavier Duarte, Song Han, Philip Harris, Sergo Jindariani, Edward Kreinar, Benjamin Kreis, Vladimir Loncar, Jennifer Ngadiuba, Maurizio Pierini, Dylan Rankin, Ryan Rivera, Sioni Summers, Nhan Tran, Zhenbin Wu. 305 [doi]
- An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate ComputingElham Azari, Aykut Dengi, Sarma B. K. Vrudhula. 305-306 [doi]
- Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGACheng Fu, Shilin Zhu, Hao Su, Ching-En Lee, Jishen Zhao. 306 [doi]
- Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAsDallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin. 306-307 [doi]
- BRISC-V: An Open-Source Architecture Design Space Exploration ToolboxSahan Bandara, Alan Ehret, Donato Kava, Michel A. Kinsy. 306 [doi]
- Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with OptimizationsVenkat Konda. 307 [doi]
- Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and EnhancementsVenkat Konda. 307 [doi]
- HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic ConversionMichael P. Kapralos, John A. Chandy. 307-308 [doi]
- Engaging Heterogeneous FPGAs in the CloudKe Zhang, Yisong Chang, Mingyu Chen 0001, Yungang Bao, Zhiwei Xu. 308 [doi]
- Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow ControlGurshaant Singh Malik, Nachiket Kapre. 308 [doi]
- Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLSSahithi Rampalli, Natasha Sehgal, Ishita Bindlish, Tanya Tyagi, Pawan Kumar. 308-309 [doi]
- Efficient Acceleration of CNNs for Semantic Segmentation on FPGAsSebastian Vogel, Jannik Springer, Andre Guntoro, Gerd Ascheid. 309 [doi]
- A FPGA Implementation of Farneback Optical Flow by High-Level SynthesisChia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou. 309 [doi]
- Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAsMikhail Asiatici, Paolo Ienne. 310-319 [doi]
- Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex CachingZhiyuan Shao, Ruoshi Li, Diqing Hu, Xiaofei Liao, Hai Jin 0001. 320-329 [doi]
- FASED: FPGA-Accelerated Simulation and Evaluation of DRAMDavid Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic. 330-339 [doi]