Abstract is missing.
- ForewordOmer Khan, Maria K. Michael, Antonio Miele, Qiaoyan Yu. [doi]
- BTI aware thermal management for reliable DVFS designsHardeep Chahal, Vasileios Tenentes, Daniele Rossi, Bashir M. Al-Hashimi. 1-6 [doi]
- Prognosis of NBTI aging using a machine learning schemeNaghmeh Karimi, Ke Huang. 7-10 [doi]
- Experimental study and analysis of soft and permanent errors in digital camerasGlenn H. Chapman, Rahul Thomas, Rohan Thomas, Israel Koren, Zahava Koren. 11-14 [doi]
- A Highly Robust Double Node Upset Tolerant latchAdam Watkins, Spyros Tragoudas. 15-20 [doi]
- Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardwareAlexander Scholl, Claus Braun, Hans-Joachim Wunderlich. 21-26 [doi]
- Construction of a soft error (SEU) hardened Latch with high critical chargeHiroki Ueno, Kazuteru Namba. 27-30 [doi]
- Design and analysis of an approximate 2D convolverKe Chen, Fabrizio Lombardi, Jie Han. 31-34 [doi]
- Combined on-line lifetime-energy optimization for asymmetric multicoresCristiana Bolchini, Matteo Carminati, Tulika Mitra, Thannirmalai Somu Muthukaruppan. 35-40 [doi]
- Effects of online fault detection mechanisms on Probabilistic Timing AnalysisChao Chen, Jacopo Panerati, Giovanni Beltrame. 41-46 [doi]
- Bounding error detection latency in safety critical systems with enhanced Execution FingerprintingMojing Liu, Brett H. Meyer. 47-52 [doi]
- Guiding Genetic Algorithms using importance measures for reliable design of embedded systemsHananeh Aliee, Stefan Vitzethum, Michael Glaß, Jürgen Teich, Emanuele Borgonovo. 53-56 [doi]
- Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failuresZaid Al-bayati, Brett H. Meyer, Haibo Zeng. 57-62 [doi]
- Cross-layer fault-tolerant design of real-time systemsSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar 0001. 63-68 [doi]
- Fault-aware sensitivity analysis for probabilistic real-time systemsLuca Santinelli, Zhishan Guo, Laurent George. 69-74 [doi]
- Low cost resilient regular expression matching on FPGAsMarcos T. Leipnitz, Eduardo Nunes de Souza, Gabriel L. Nazar. 75-80 [doi]
- In-place LUT polarity inVersion to mitigate soft errors for FPGAsJuexiao Su, Ju-Yueh Lee, Chang Wu, Lei He. 81-86 [doi]
- Detecting intermittent resistive faults in digital CMOS circuitsHassan Ebrahimi, Alireza Rohani, Hans G. Kerkhoff. 87-90 [doi]
- Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPUXabier Iturbe, Balaji Venu, Emre Ozer. 91-96 [doi]
- Efficient utilization of hierarchical iJTAG networks for interrupts managementAhmed Ibrahim, Hans G. Kerkhoff. 97-102 [doi]
- Error recovery through partial value similarityAbdulaziz Eker, Oguz Ergin. 103-106 [doi]
- In-field functional test programs development flow for embedded FPUsRiccardo Cantoro, D. Piumatti, Paolo Bernardi, Sergio de Luca, Alessandro Sansonetti. 107-110 [doi]
- Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegramsFilippo Giuliani, Marco Ottavi, Gian-Carlo Cardarilli, Marco Re, Luca Di Nunzio, Rocco Fazzolari, Antimo Bruno, Francesco Zuliani. 111-114 [doi]
- CoBRA: Low cost compensation of TSV failures in 3D-NoCRonak Salamat, Masoumeh Ebrahimi, Nader Bagherzadeh, Freek Verbeek. 115-120 [doi]
- A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCsAmir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis. 121-126 [doi]
- An adaptive routing algorithm to improve lifetime reliability in NoCs architectureJuman Alshraiedeh, Avinash Kodi. 127-130 [doi]
- A novel method for SEE validation of complex SoCs using Low-Energy Proton beamsGianluca Furano, Stefano Di Mascio, Tomasz Szewczyk, Alessandra Menicucci, Luigi Campajola, Francesco Di Capua, Andrea Fabbri, Marco Ottavi. 131-134 [doi]
- Reliable PUF design using failure patterns from time-controlled power gatingXiaolin Xu, Daniel E. Holcomb. 135-140 [doi]
- Side channel attacks on STTRAM and low-overhead countermeasuresAnirudh Iyengar, Swaroop Ghosh, Nitin Rathi, Helia Naeimi. 141-146 [doi]
- On meta-obfuscation of physical layouts to conceal design characteristicsVinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu. 147-152 [doi]
- Can flexible, domain specific programmable logic prevent IP theft?Xiaotong Cui, Kaijie Wu 0001, Siddharth Garg, Ramesh Karri. 153-157 [doi]