Sang H. Dhong - researchr alias

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Viewing Publication 1 - 29 from 29

2015

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technologyHenry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang. cicc 2015: 1-3 [doi]

2014

2013

Prospective for nanowire transistorsJean-Pierre Colinge, Sang H. Dhong. cicc 2013: 1-8 [doi]

2 per MBMing-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong. cicc 2013: 1-4 [doi]

2008

Challenges at 45nm and beyondDan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong. iccad 2008: 7 [doi]

2007

Implementation of the 65nm Cell Broadband EngineMack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino. cicc 2007: 717-720 [doi]

Cell Broadband Engine Processor Design MethodologyOsamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, Peter Hofstee, C. J. Johnson, Stephen D. Posluszny. cicc 2007: 711-716 [doi]

2006

A cycle accurate power estimation toolRajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong. aspdac 2006: 867-870 [doi]

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processorHwa-Joon Oh, Silvia M. Müller, Christian Jacobi 0002, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong. jssc, 41(4):759-771, 2006. [doi]

Circuit Design Techniques for a First-Generation Cell Broadband Engine ProcessorJames D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen. jssc, 41(8):1692-1706, 2006. [doi]

2005

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell ProcessorToru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara. micro, 25(5):30-38, 2005. [doi]

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL ProcessorSilvia M. Müller, Christian Jacobi 0002, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong. arith 2005: 59-67 [doi]

Power-Conscious Design of the Cell Processor s Synergistic Processor ElementOsamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman. micro, 25(5):10-18, 2005. [doi]

The circuit design of the synergistic processor element of a CELL processorOsamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman. iccad 2005: 111-117

2000

Custom circuit design as a driver of microprocessor performanceDavid H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel. ibmrd, 44(6):799-822, 2000. [doi]

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macroOsamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki. jssc, 35(11):1673-1679, 2000. [doi]

1999

A 1-GHz logic circuit family with sense amplifiersOsamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong. jssc, 34(5):616-622, 1999. [doi]

1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz MicroprocessorDavid F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz. vts 1998: 234-238 [doi]

Designing for a gigahertz [guTS integer processor]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi. micro, 18(3):66-74, 1998. [doi]

Design methodology for a 1.0 GHz microprocessorStephen D. Posluszny, N. Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, K. Lee, D. Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo. In ICCD. 1998: 17-23 [doi]

A 690 ps read-access latency register file for a GHz integer microprocessorOsamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, N. Aoki. In ICCD. 1998: 6-10 [doi]

1995

A low-noise TTL-compatible CMOS off-chip driver circuitSang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata. ibmrd, 39(1-2):105-112, 1995.

A variable precharge voltage sensingToshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira. jssc, 30(1):25-28, January 1995. [doi]

A 64Kb - 32 DRAM for graphics applicationsToshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura. ibmrd, 39(1-2):43-50, 1995.

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1995

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