Table of Contents

• A novel switched-capacitor-filter based low-area and fast-locking PLLMezyad Amourah, Morgan Whately. 1-6 [doi]
• A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOSBehzad Dehlaghi, Anthony Chan Carusone. 1-4 [doi]
• Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCsWon Ho Choi, Hoon Ki Kim, Chris H. Kim. 1-4 [doi]
• A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performanceVahid Behravan, Shuo Li, Neil E. Glover, Chia-Hung Chen, Mohammed Shoaib, Gabor C. Temes, Patrick Yin Chiang. 1-4 [doi]
• 2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibrationYeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun. 1-4 [doi]
• A circuit designer's guide to 5G mm-waveAli M. Niknejad, Siva V. Thyagarajan, Elad Alon, Yanjie Wang, Christopher D. Hull. 1-8 [doi]
• A millimeter-wave fully differential transformer-based passive reflective-type phase shifterTso-Wei Li, Hua Wang. 1-4 [doi]
• A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOSMayank Raj, Manuel Monge, Azita Emami. 1-4 [doi]
• A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cellsJihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine. 1-4 [doi]
• Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOSMinki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De. 1-4 [doi]
• Phase-locked frequency synthesis and modulation for modern wireless transceiversWoogeun Rhee. 1-75 [doi]
• A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variationsArijit Banerjee, Jacob Breiholz, Benton H. Calhoun. 1-4 [doi]
• A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOSJunlei Zhao, Matteo Bassi, Andrea Mazzanti, Francesco Svelto. 1-4 [doi]
• A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nmRakesh Kumar Palani, Ramesh Harjani. 1-4 [doi]
• Session 7 - Advances in biomedial sensor systemsChristophe Antoine, Rikky Muller. 1 [doi]
• Session 11 - Advanced techniques for power amplifier transceiver front-endsYanjie Wang, Hua Wang. 1 [doi]
• A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technologyKe Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang. 1-4 [doi]
• A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nmBurak Erbagci, Nail Etkin Can Akkaya, Craig Teegarden, Ken Mai. 1-4 [doi]
• Characterization and simulation methodology for time-dependent variability in advanced technologiesPieter Weckx, Ben Kaczer, Praveen Raghavan, Jacopo Franco, Marco Simicic, Philippe J. Roussel, Dimitri Linten, Aaron Thean, Diederik Verkest, Francky Catthoor, Guido Groeseneken. 1-8 [doi]
• A mixed-domain modeling method for RF systemsZhimiao Chen, Zhixing Liu, Lei Liao, Ralf Wunderlich, Stefan Heinen. 1-4 [doi]
• Session 2 - Low power analogShahrzad Naraghi, Alessandro Piovaccari. 1 [doi]
• Session 22 - High frequency analog techniquesTimothy M. Hancock, Jorge Grilo. 1 [doi]
• Methods for finding globally maximum-efficiency impedance matching networks with lossy passivesChandraKanth R. Chappidi, Kaushik Sengupta. 1-4 [doi]
• Monolithic very high frequency GaN switched-mode power convertersDragan Maksimovic, Yuanzhe Zhang, Miguel Rodriguez. 1-4 [doi]
• An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalizationHyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae. 1-4 [doi]
• Ultra-low power multi-channel data conversion with a single SAR ADC for mobile sensing applicationsWenjuan Guo, Youngchun Kim, Ahmed H. Tewfik, Nan Sun. 1-4 [doi]
• A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodologyAmr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd. 1-4 [doi]
• A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoCYuan-Hung Chung, Che-Hung Liao, Chun-Wei Lin, Yi-Shing Shih, Chin-Fu Li, Meng-Hsiung Hung, Ming-Chung Liu, Pi-An Wu, Jui-Lin Hsu, Ming-Yeh Hsu, Sheng-Hao Chen, Po-Yu Chang, Chih-Hao Chen, Yu-hsien Chang, Jun-Yu Chen, Tao-Yao Chang, George Chien. 1-8 [doi]
• Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technologyHenry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang. 1-3 [doi]
• A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularityAhmed I. Hussein, Shadi Saberi, Jeyanandh Paramesh. 1-4 [doi]
• Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome themPeter R. Kinget. 1-8 [doi]
• A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOSJie Fang, Shankar Thirunakkarasu, Xuefeng Yu, Fabian Silva-Rivas, Kwang-Young Kim, Chaoming Zhang, Frank Singor. 1-4 [doi]
• A configurable 5.9 μW analog front-end for biosignal acquisitionTan Yang, Junjie Lu, M. Shahriar Jahan, Kelly Griffin, Jeremy Langford, Jeremy Holleman. 1-4 [doi]
• A 0.622-10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOSSagar Ray, Mona M. Hella. 1-4 [doi]
• Computing in 3DPaul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa. 1-6 [doi]
• A power electronics unit to drive piezoelectric actuators for flying microrobotsMario Lok, Xuan Zhang, Elizabeth Farrell Helbling, Robert J. Wood, David M. Brooks, Gu-Yeon Wei. 1-4 [doi]
• A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensingJohn K. DeBrosse, Thomas M. Maffitt, Yutaka Nakamura, Guenole Jan, Po-Kang Wang. 1-3 [doi]
• A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOSTzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen. 1-4 [doi]
• MAPP: The Berkeley Model and Algorithm Prototyping PlatformTianshi Wang, Aadithya V. Karthik, Bichen Wu, Jian Yao, Jaijeet Roychowdhury. 1-8 [doi]
• Session 20 - Manufacturing beyond moore's lawPhilippe Jansen, Ramnath Venkatraman. 1 [doi]
• A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensationDerui Kong, Sang Min Lee, Shahin Mehdizad Taleie, Michael Joseph McGowan, Dongwon Seo. 1-4 [doi]
• An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifierBongjin Kim, Hoonki Kim, Chris H. Kim. 1-4 [doi]
• Dynamic and leakage power reduction of ASICs using configurable threshold logic gatesJinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula. 1-4 [doi]
• Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signalsSomnath Kundu, Bongjin Kim, Chris H. Kim. 1-4 [doi]
• Physics-based compact models for insulated-gate field-effect biosensors, landau-transistors, and thin-film solar cellsMuhammad A. Alam, Piyush Dak, Muhammad A. Wahab, Xingshu Sun. 1-8 [doi]
• 2-4 GHz Q-tunable LC bandpass filter with 172-dBHz peak dynamic range, resilient to +15-dBm out-of-band blockerLaya Mohammadi, Kwang-Jin Koh. 1-4 [doi]
• A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMTSungwon Chung, Hae-Seung Lee. 1-4 [doi]
• Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospectsRobert Aitken, Tetsuya Iizuka. 1 [doi]
• Session 19 - Power managementHoi Lee, Jeff Morroni. 1-2 [doi]
• 2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOSPavan Kumar, Vaibhav A. Vaidya, Harish Krishnamurthy, Stephen T. Kim, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De. 1-4 [doi]
• Session 4 - Frequency and phase generation techniquesFa Foster Dai, Swaminathan Sankaran. 1 [doi]
• 2 SAR ADC in 0.13μm CMOS for high precision nerve recordingAnh Tuan Nguyen, Jian Xu, Zhi Yang. 1-4 [doi]
• A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage rangeLoai G. Salem, Patrick P. Mercier. 1-4 [doi]
• A soft-error hardened process portable embedded microprocessorVinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth. 1-4 [doi]
• A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibrationTimothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman. 1-4 [doi]
• Session 25 - 20 Gb/s transmitters and receiversJun Cao, Shahriar Mirabbasi. 1 [doi]
• Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOSFan Yang, Philip K. T. Mok. 1-4 [doi]
• A compact, high linearity 40GS/s track-and-hold amplifier in 90nm SiGe technologyDeeksha Lal, Morteza Abbasi, David S. Ricketts. 1-4 [doi]
• Wireless synchronization of mm-wave arrays in 65nm CMOSCharles Chen, Aydin Babakhani. 1-4 [doi]
• A high-performance, yet simple to design, digital-friendly type-I PLLAhmad Sharkia, Sankaran Aniruddhan, Sudip Shekhar, Shahriar Mirabbasi. 1-4 [doi]
• MAA evolution: Common access/backhaul reference platformAli Sadri. 1-32 [doi]
• A novel low cost, high performance and reliable silicon interposerFarhang Yazdani. 1-6 [doi]
• Materials challenges for III-V/Si co-integrated CMOSD. K. Sadana, C. W. Cheng, B. Wacaser, W. Spratt, K. T. Shiu, Stephen W. Bedell. 1-6 [doi]
• ADC trends and impact on SAR ADC architecture and analysisJeffrey Fredenburg, Michael P. Flynn. 1-8 [doi]
• Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited)Srinivasa Banna. 1-8 [doi]
• Session 6 - Analog circuits using digital cellsJing Yang, Arijit Raychowdhury. 1 [doi]
• A 2-24GHz 360° full-span differential vector modulator phase rotator with transformer-based poly-phase quadrature networkTso-Wei Li, Jong Seok Park, Hua Wang. 1-4 [doi]
• Multiphase RF techniques in CMOS: Applied to beam-forming and full duplex receivers: CICC 2015 educational sessionBram Nauta. 1-147 [doi]
• A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibrationKareem Ragab, Nan Sun. 1-4 [doi]
• Design of PVT tolerant inverter based circuits for low supply voltagesRamesh Harjani, Rakesh Kumar Palani. 1-8 [doi]
• SAR ADCs in parallel [time-interleaved] converter arraysRon Kapusta. 1-86 [doi]
• A low TC, supply independent and process compensated current referenceChundong Wu, Wang Ling Goh, Chiang Liang Kok, Wanlan Yang, Liter Siek. 1-4 [doi]
• Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widthsXue Wu, Kaushik Sengupta. 1-4 [doi]
• An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnectsTakashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo. 1-4 [doi]
• A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technologyDongseok Shin, Sanjay Raman, Kwang-Jin Koh. 1-4 [doi]
• Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation spaceShupeng Sun, Xin Li. 1-4 [doi]
• All-digital SoC thermal sensor using on-chip high order temperature curvature correctionMehdi Saligane, Mahmood Khayatzadeh, Yiqun Zhang, Seokhyeon Jeong, David Blaauw, Dennis Sylvester. 1-4 [doi]
• A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoMAmir Nikpaik, Abdolreza Nabavi, Amir Hossein Masnadi Shirazi, Sudip Shekhar, Shahriar Mirabbasi. 1-4 [doi]
• 2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEMShuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu. 1-4 [doi]
• Resonant wireless power transfer technology & integration roadmapFrancesco Carobolante. 1-96 [doi]
• Session 3 - Optical interconnect and reliability enhancement techniquesTetsuya Iizuka, Takahiro Yamaguchi. 1 [doi]
• Timing in-situ monitors: Implementation strategy and applications resultsA. Benhassain, F. Cacho, V. Huard, M. Saliva, L. Anghel, C. R. Parthasarathy, A. Jain, F. Giner. 1-4 [doi]
• A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealitiesJintao Zhang, Liechao Huang, Zhuo Wang, Naveen Verma. 1-4 [doi]
• A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implantsCheng Huang, Toru Kawajiri, Hiroki Ishikuro. 1-4 [doi]
• Session 23 - Modeling emerging devicesChenjie Gu, Hidetoshi Onodera. 1 [doi]
• A Cartesian feedback-feedforward transmitter IC in 130nm CMOSSungmin Ock, Hyejeong Song, Ranjit Gharpurey. 1-4 [doi]
• A few behavioral modeling options for balancing verification coverage and credibilityJess Chen. 1-115 [doi]
• A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOSJong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae. 1-4 [doi]
• 2, > ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoringSeongjong Kim, Mingoo Seok. 1-4 [doi]
• A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOSJoo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee. 1-4 [doi]
• A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processorHaruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, K. Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
• A full-duplex wireless integrated transceiver for implant-to-air data communicationsSeyed Abdollah Mirbozorgi, Hadi Bahrami, Mohamad Sawan, Leslie A. Rusch, Benoit Gosselin. 1-4 [doi]
• TM microprocessor (broadwell)Praveen Mosalikanti, Nasser A. Kurd, Christopher Mozak, Takao Oshita. 1-4 [doi]
• Practical considerations for application specific time interleaved ADCsAaron Buchwald. 1-8 [doi]
• A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresisChen Zhang, Muhammad Awais Bin Altaf, Jerald Yoo Masdar. 1-4 [doi]
• A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposerJie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P. D., Hao Yu. 1-4 [doi]
• A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technologyYu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, Cheng-Hsiang Hsieh, Tung-Tsun Chen. 1-4 [doi]
• A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studiesJongyeon Kim, An Chen, Behtash Behin-Aein, Saurabh Kumar, Jian-Ping Wang, Chris H. Kim. 1-4 [doi]
• Efficiency improvement techniques for RF power amplifiers in deep submicron CMOSAritra Banerjee, Rahmi Hezar, Lei Ding. 1-4 [doi]
• A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensorsShanshan Dai, Jacob K. Rosenstein. 1-4 [doi]
• A voltage doubling passive rectifier/regulator circuit for biomedical implantsEdward K. F. Lee. 1-4 [doi]
• Session 18 - Data converter techniquesJohn McNeill, Abhishek Bandyopadhyay. 1 [doi]
• Design considerations of HBM stacked DRAM and the memory architecture extensionDong Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung-whan Kim, Jong-Ho Kang, Jaejin Lee, Jun Hyun Chun. 1-8 [doi]
• An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOSHundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic, Ramesh Harjani. 1-4 [doi]
• 390-640MHz tunable oscillator based on phase interpolation with -120dBc/Hz in-band noiseXu Meng, Lianhong Zhou, Fujiang Lin, Chun-Huat Heng. 1-4 [doi]
• Supply noise induced jitter modeling and optimization for high-speed interfacesDan Oh, Yujeong Shim, Guang Chen. 1-42 [doi]
• A field-programmable noise-canceling wideband receiver with high-linearity hybrid class-AB-C LNTAsJianxun Zhu, Peter R. Kinget. 1-4 [doi]
• A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operationJoon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae. 1-4 [doi]
• Arria™ 10 device architectureJeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Shumarayev, Tim Hoang, Allen Chan, Dong Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang. 1-8 [doi]
• A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 HzHui Wang, Patrick P. Mercier. 1-4 [doi]
• 3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%Xingyi Hua, Ramesh Harjani. 1-4 [doi]
• Embedded cooling technologies for densely integrated electronic systemsThomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, Ravi Gutala, Colman Cheung, Arifur Rahman, Muhannad S. Bakir. 1-8 [doi]
• A 5-115V efficiency-enhanced synchronous LED driver with adaptive resonant timing controlZhidong Liu, Hoi Lee. 1-4 [doi]
• A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitterAhmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu. 1-4 [doi]
• Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technologyJunho Cheon, Insoo Lee, Changyong Ahn, Milos Stanisavljevic, Aravinthan Athmanathan, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou, Min Chul Shin, Taekseung Kim, Jong-Ho Kang, Jun Hyun Chun. 1-4 [doi]
• Sub-sampling PLL techniquesXiang Gao, Eric A. M. Klumperink, Bram Nauta. 1-8 [doi]
• A low energy SRAM-based physically unclonable function primitive in 28 nm CMOSAdam Neale, Manoj Sachdev. 1-4 [doi]
• A fully synthesized 0.4V 77dB SFDR reprogrammable SRMC filter using digital standard cellsJun Liu, Ahmed Fahmy, Taewook Kim, Nima Maghari. 1-4 [doi]
• An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency dividerDongil Lee, Tae-Ho Lee, Yong Hun Kim, Young-Ju Kim 0001, Lee-Sup Kim. 1-4 [doi]
• A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output rippleDanzhu Lu, Suyi Yao, Bin Shao. 1-4 [doi]
• A 0.1-5.0GHz self-calibrated SDR transmitter with -62.6dBc CIM3 in 65nm CMOSYun Yin, Yanqiang Gao, Zhihua Wang, Baoyong Chi. 1-4 [doi]
• A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instrumentsF. Hsiao, A. Tang, Y. Kim, Brian Drouin, Goutam Chattopadhyay, M.-C. Frank Chang. 1-3 [doi]
• Advanced wireless power and data transmission techniques for implantable medical devicesHyung-Min Lee, Mehdi Kiani, Maysam Ghovanloo. 1-8 [doi]
• A 28-GHz inverse class-F power amplifier with coupled-inductor based harmonic impedance modulatorSeyed Yahya Mortazavi, Kwang-Jin Koh. 1-4 [doi]
• A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reductionLong Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun. 1-4 [doi]
• Symmetry breaking in the drain current of multi-finger transistorsNing Lu, Sungjae Lee, Richard A. Wachnik. 1-4 [doi]
• A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap referenceRaveesh Magod, Naveen Suda, Vadim Ivanov, Ravi Balasingam, Bertan Bakkaloglu. 1-4 [doi]
• Recent advances in Ga N MMIC technologyNicholas J. Kolias. 1-5 [doi]
• A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine spaceShouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. 1-4 [doi]
• A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interfaceWei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, Sheau Jiung Lee, Mau-Chung Frank Chang. 1-4 [doi]
• Session 14 - Emerging technology, power and coolingArif Rahman, Aurangzeb Khan. 1-4 [doi]
• Holisitic device exploration for 7nm nodePraveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, A. Mocuta, D. Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, A. Steegen. 1-5 [doi]
• A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output networkJong Seok Park, Song Hu, Yanjie Wang, Hua Wang. 1-4 [doi]
• Session 9 - Advanced simulation techniquesColin McAndrew, Larry Nagel. 1 [doi]
• Low dropout regulatorsPavan Kumar Hanumolu. 1-37 [doi]
• A 3.9 mW, 35-44/41-59.5 GHz distributed injection locked frequency dividerAlireza Imani, Hossein Hashemi. 1-4 [doi]
• A 1A, 20MHz/100MHz dual-inductor 4-output buck converter with fully-integrated bond-wire-based output filters for ripple reductionYongjie Jiang, Ayman A. Fayed. 1-4 [doi]
• 2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuraciesGolam R. Chowdhury, Arjang Hassibi. 1-4 [doi]
• A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOSShuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang. 1-4 [doi]