Abstract is missing.
- Designing a Testable System on a ChipStephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin G. Stawiasz. 2-7 [doi]
- Hierarchical Test Access Architecture for Embedded Cores in an Integrated CircuitDebashis Bhattacharya. 8-14 [doi]
- Parallelism in Structural Fault Testing of Embedded CoresMehrdad Nourani, Christos A. Papachristou. 15-21 [doi]
- Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing ParadigmOvidio V. Maiuri, Will R. Moore. 22-27 [doi]
- Signal Integrity Problems in Deep Submicron Arising from Interconnects between CoresPetra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams. 28-33 [doi]
- Automatic Test Pattern Generation for Crosstalk Glitches in Digital CircuitsKyung Tek Lee, Clay Nordquist, Jacob A. Abraham. 34-41 [doi]
- Fault Detection and Diagnosis of Interconnects of Random Access MemoriesJun Zhao, Fred J. Meyer, Fabrizio Lombardi. 42-47 [doi]
- A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault DiagnosisKazuki Shigeta, Toshio Ishiyama. 48-53 [doi]
- Performance Test Case Generation for MicroprocessorsPradip Bose. 54-61 [doi]
- COMPACT: A Hybrid Method for Compressing Test DataMasahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi. 62-69 [doi]
- Synthesis of Zero-Aliasing Elementary-Tree Space CompactorsBahram Pouya, Nur A. Touba. 70-77 [doi]
- Bit Serial Pattern Generation and Response Compaction Using Arithmetic FunctionsAlbrecht P. Stroele. 78-85 [doi]
- Ground Bounce Considerations in DC Parametric Test Generation Using Boundary ScanAmitava Majumdar, Michio Komoda, Tim Ayres. 86-91 [doi]
- Self-Timed Boundary-Scan Cells for Multi-Chip Module TestT. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos. 92-97 [doi]
- Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and ChipsKamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III. 98-105 [doi]
- IDDQ Testing of Opens in CMOS SRAMsVíctor H. Champac, José Castillejos, Joan Figueras. 106-111 [doi]
- A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging FaultTsuyoshi Shinogi, Terumine Hayashi. 112-117 [doi]
- Experimental Results for IDDQ and VLV TestingJonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey. 118-125 [doi]
- Nonlinear Analog DC Fault Simulation by One-Step RelaxationMichael W. Tian, C.-J. Richard Shi. 126-131 [doi]
- Enhancing Test Effectiveness for Analog Circuits Using Synthesized MeasurementsPramodchandran N. Variyam, Abhijit Chatterjee. 132-137 [doi]
- Effect of Noise on Analog Circuit TestingMadhu K. Iyer, Michael L. Bushnell. 138-144 [doi]
- Hierarchical Statistical Inference Model for Specification Based Testing of Analog CircuitsHeebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi. 145-151 [doi]
- Robustly Testable Array Multipliers under Realistic Sequential Cell Fault ModelMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 152-157 [doi]
- On Synchronizing Sequences and Test Sequence PartitioningIrith Pomeranz, Sudhakar M. Reddy. 158-167 [doi]
- On Removing Redundant Faults in Synchronous Sequential CircuitsXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy. 168-175 [doi]
- Undetectable Fault Removal of Sequential Circuits Based on Unreachable StatesHiroyuki Yotsuyanagi, Kozo Kinoshita. 176-183 [doi]
- Analysis of Failures in Deep Submicron SRAM CellsPinaki Mazumder. 184-187 [doi]
- Efficient Path Selection for Delay Testing Based on Partial Path EvaluationSeiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro. 188-193 [doi]
- On Delay-Untestable Paths and Stuck-Fault RedundancySubhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell. 194-199 [doi]
- Improving Path Delay Fault Testability by Path RemovalUwe Sparmann, Lars Köller. 200-209 [doi]
- Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan InsertionGanapathy Parthasarathy, Michael L. Bushnell. 210-217 [doi]
- Design of Phase Shifters for BIST ApplicationsJanusz Rajski, Jerzy Tyszer. 218-224 [doi]
- Distributed Generation of Weighted Random PatternsJacob Savir. 225-233 [doi]
- High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz MicroprocessorDavid F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz. 234-238 [doi]
- Impedance Mismatch and Lumped Capacitance Effects in High Frequency TestingIboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska, Fartoumi M. Hossein, Patrick Vincent. 239-244 [doi]
- Mixed Signal DFT at GHz FrequenciesRalph Mason, Shing Ma. 245-253 [doi]
- Using Verification Technology for Validation Coverage Analysis and Test GenerationDinos Moundanos, Jacob A. Abraham. 254-259 [doi]
- On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor ArraysLi-C. Wang, Magdy S. Abadir, Jing Zeng. 260-265 [doi]
- A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended ProbRongchang Yan, Bruce C. Kim. 266-273 [doi]
- A Study on the Utility of Using Expected Quality Level as a Design for Testability MetricDouglas Williams, F. Joel Ferguson, Tracy Larrabee. 274-282 [doi]
- Sampling Techniques of Non-Equally Probable Faults in VLSI SystemFernando M. Gonçalves, João Paulo Teixeira. 283-288 [doi]
- Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect CoverageIrith Pomeranz, Sudhakar M. Reddy. 289-295 [doi]
- Fast Self-Recovering ControllersAndre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich. 296-302 [doi]
- Applying Built-In Self-Test to Majority Voting Fault Tolerant CircuitsCharles E. Stroud, Joe K. Tannehill Jr.. 303-308 [doi]
- Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin CodesDebaleena Das, Nur A. Touba. 309-317 [doi]
- Test Reuse at System LevelJosé M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman. 318-319 [doi]
- Testing MEMSJean-Michel Karam, Marcelo Lubaszewski, S. Blanton, Andrew Richardson. 320-321 [doi]
- Validation and Test Problems for Cross Talk NoiseSandip Gupta, Craig Gleason. 322-323 [doi]
- A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay TestingEgor S. Sogomonyan, Adit D. Singh, Michael Gössel. 324-331 [doi]
- Low Cost Partial Scan Design: A High Level Synthesis ApproachMarie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe. 332-340 [doi]
- Partial Reset and Scan for Flip-Flops Based on States Requirement for Test GenerationHsing-Chung Liang, Chung-Len Lee, Jwu E. Chen. 341-347 [doi]
- Novel Single and Double Output TSC Berger Code CheckersXrysovalantis Kavousianos, Dimitris Nikolos. 348-353 [doi]
- A Structural Approach for Space Compaction for Concurrent Checking and BISTMarkus Seuring, Michael Gössel, Egor S. Sogomonyan. 354-361 [doi]
- Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under CheckArsen Kuchukyan. 362-369 [doi]
- Design-For-Testability for Switched-Current CircuitsFlorence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin. 370-375 [doi]
- A Design for Testability Study on a High Performance Automatic Gain Control CircuitA. Lechner, Andrew Richardson, B. Hermes, Michael J. Ohletz. 376-385 [doi]
- Decreasing the Sensitivity of ADC Test Parameters by Means of WobblingR. de Vries, Augustus J. E. M. Janssen. 386-393 [doi]
- A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache TagsSultan M. Al-Harbi, Sandeep K. Gupta. 394-400 [doi]
- Fault Models and Tests for Two-Port MemoriesA. J. van de Goor, Said Hamdioui. 401-410 [doi]
- An Approach to Modeling and Testing Memories and Its Application to CAMsPiotr R. Sidorowicz, Janusz A. Brzozowski. 411-417 [doi]
- Built-In Self Testing of Sequential Circuits Using Precomputed Test SetsVikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray. 418-423 [doi]
- On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential CircuitsFulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda. 424-429 [doi]
- Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern GeneratorsBruce F. Cockburn, Albert L.-C. Kwong. 430-439 [doi]
- A Nonenumerative ATPG for Functionally Sensitizable Path Delay FaultsDimitrios Karayiannis, Spyros Tragoudas. 440-445 [doi]
- New Techniques for Deterministic Test Pattern GenerationIlker Hamzaoglu, Janak H. Patel. 446-452 [doi]
- A Test Pattern Generation Methodology for Low-Power ConsumptionFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 453-459 [doi]
- Best Methods for At-Speed Testing?Peter C. Maxwell, Steve Baird, Wayne M. Needham, Al Crouch, Phil Nigh. 460-461 [doi]
- An Introduction to RF Testing: Device, Method and SystemJeffrey S. Kasten. 462-469 [doi]
- Where We Might Stumble with Embedded-System TestKeerthi Heragu. 470 [doi]