Roope Kaivola - researchr alias

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Viewing Publication 1 - 23 from 23

2021

Hardware Security Leak Detection by Symbolic SimulationNeta Bar Kama, Roope Kaivola. FMCAD 2021: 34-41 [doi]

2013

Relational STE and theorem proving for formal verification of industrial circuit designsJohn W. O'Leary, Roope Kaivola, Tom Melham. FMCAD 2013: 97-104 [doi]

2011

Intel Core:::TM::: i7 Processor Execution Engine Validation in a Functional Language Based Formal FrameworkRoope Kaivola. PADL 2011: 1 [doi]

2009

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine ValidationRoope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir Frolov, Erik Reeber, Armaghan Naik. cav 2009: 414-429 [doi]

2005

Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive InvariantsRoope Kaivola. cav 2005: 170-184 [doi]

Formal verification of high-level conformance with symbolic simulationRoope Kaivola, Armaghan Naik. hldvt 2005: 153-159 [doi]

Stepwise Development of Process-Algebraic Specifications in Decorated Trace SemanticsT. Karvi, Tienari Tienari, Roope Kaivola. fmsd, 26(3):293-317, 2005. [doi]

2003

Proof engineering in the large: formal verification of Pentium?4 floating-point dividerRoope Kaivola, Katherine R. Kohatsu. STTT, 4(3):323-334, 2003. [doi]

2002

Formal Verification of the Pentium ® 4 Floating-Point MultiplierRoope Kaivola, Naren Narasimhan. date 2002: 20-27 [doi]

2001

Proof Engineering in the Large: Formal Verification of Pentium:::®::: 4 Floating-Point DividerRoope Kaivola, Katherine R. Kohatsu. charme 2001: 196-211 [doi]

(R) 4 multiplierRoope Kaivola, Naren Narasimhan. hldvt 2001: 115-120 [doi]

2000

Formal verification of iterative algorithms in microprocessorsMark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger. dac 2000: 201-206 [doi]

Divider Circuit Verification with Model Checking and Theorem ProvingRoope Kaivola, Mark Aagaard. tphol 2000: 338-355

1998

Axiomatising Extended Computation Tree LogicRoope Kaivola. TCS, 190(1):41-60, 1998. [doi]

1997

Using Compositional Preorders in the Verification of Sliding Window ProtocalRoope Kaivola. cav 1997: 48-59

1996

Axiomatising Extended Computation Tree LogicRoope Kaivola. caap 1996: 87-101

Fixpoints for Rabin Tree Automata Make Complementation EasyRoope Kaivola. icalp 1996: 312-323

1995

Axiomatising Linear Time Mu-calculusRoope Kaivola. concur 1995: 423-437

On Modal mu-Calculus and Büchi Tree AutomataRoope Kaivola. ipl, 54(1):17-22, 1995. [doi]

A Simple Decision Method for the Linear Time Mu-calculusRoope Kaivola. strict 1995: 190-204 [doi]

1992

Compositional Model Checking for Linear-Time Temporal LogicRoope Kaivola. cav 1993: 248-259

The Weakest Compositional Semantic Equivalence Preserving Nexttime-less Linear temporal LogicRoope Kaivola, Antti Valmari. concur 1992: 207-221

1991

Using Truth-Preserving Reductions to Improve the Clarity of Kripke-ModelsRoope Kaivola, Antti Valmari. concur 1991: 361-375

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