Naren Narasimhan - researchr alias

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Viewing Publication 1 - 10 from 10

2009

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine ValidationRoope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir Frolov, Erik Reeber, Armaghan Naik. cav 2009: 414-429 [doi]

2004

Reference model based RTL verification: an integrated approachWilliam N. N. Hung, Naren Narasimhan. hldvt 2004: 9-13 [doi]

2002

Formal Verification of the Pentium ® 4 Floating-Point MultiplierRoope Kaivola, Naren Narasimhan. date 2002: 20-27 [doi]

2001

(R) 4 multiplierRoope Kaivola, Naren Narasimhan. hldvt 2001: 115-120 [doi]

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level SynthesisNaren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri. fmsd, 19(3):237-273, 2001.

1998

On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis SystemNaren Narasimhan, Ranga Vemuri. tphol 1998: 367-386

Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesisNaren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri. In ICCD. 1998: 392-399 [doi]

1996

Rapid Prototyping of Reconfigurable CoprocessorsNaren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri. asap 1996: 303-312 [doi]

Specification of Control Flow Properties for Verification of Synthesized VHDL DesignsNaren Narasimhan, Ranga Vemuri. FMCAD 1996: 327-345

Synchronous Controller Models for Synthesis from Communicating VHDL ProcessesNaren Narasimhan, Ranga Vemuri, Jay Roy. vlsid 1996: 198-204 [doi]

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