Specification of Control Flow Properties for Verification of Synthesized VHDL Designs

Naren Narasimhan, Ranga Vemuri. Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. In Mandayam K. Srivas, Albert John Camilleri, editors, Formal Methods in Computer-Aided Design, First International Conference, FMCAD 96, Palo Alto, California, USA, November 6-8, 1996, Proceedings. Volume 1166 of Lecture Notes in Computer Science, pages 327-345, Springer, 1996.

Abstract

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