Abstract is missing.
- An Architectural Design For Parallel Fractal CompressionKevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens. 3-11 [doi]
- A Decomposition Method For Efficient Use Of Distributed Supercomputers For Finite Element ApplicationsValerie E. Taylor, Jian Chen, Thomas Canfield, Rick L. Stevens. 12-24 [doi]
- Kestrel: A Programmable Array for Sequence AnalysisJeffrey D. Hirschberg, Richard Hughey, Kevin Karplus, Don Speck. 25-34 [doi]
- Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCTHyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.. 35 [doi]
- A New Euclidean Division Algorithm For Residue Number SystemsJean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller. 45-54 [doi]
- Radix-4 Vectoring Cordic Algorithm And ArchitecturesJulio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera. 55-64 [doi]
- Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics PipelineKevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga. 65-71 [doi]
- Efficient Finite Field Serial/Parallel MultiplicationLeilei Song, Keshab K. Parhi. 72 [doi]
- A New FFT Architecture and Chip Design for Motion Compensation based on Phase CorrelationColin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods. 83-92 [doi]
- Area-Efficient Parallel FIR Digital Filter ImplementationsDavid A. Parker, Keshab K. Parhi. 93-111 [doi]
- A Flexible Motion Estimation Chip for Variable Size Block MatchingJan Peter Berns, Tobias G. Noll. 112-121 [doi]
- A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion EstimationHangu Yeo, Yu Hen Hu. 122 [doi]
- Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained ResourcesJürgen Teich, Lothar Thiele, Li Zhang. 131-144 [doi]
- An Abstract Model for a Low Cost SIMD ArchitecturePascal Faudemay, Laurent Winckel. 145-154 [doi]
- Automatic Generation of Modular MappingsHyuk-Jae Lee, José A. B. Fortes. 155-164 [doi]
- High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the PipeliningMontserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata. 165 [doi]
- Monitoring and Debugging a Hard Real-Time Distributed Computer for Aircraft IndustryNicolas Hubart. 175-182 [doi]
- Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian EliminationShietung Peng, Stanislav Sedukhin, Igor S. Sedukhin. 183-192 [doi]
- A Common Architecture For The DWT and IDWTMohan Vishwanath, Robert Michael Owens. 193-198 [doi]
- Overcoming chip-to-chip delays and clock skewsGuy Even, Ami Litman. 199-208 [doi]
- Diagnosis Algorithm for Mobility-Oriented SystemPatrick Trane. 209-220 [doi]
- A VLSI System Architecture For Real-Time Intelligent Decision MakingMinesh I. Patel, N. Ranganathan. 221-230 [doi]
- Microphone Array for Hearing Aid and Speech Enhancement ApplicationsA. Wang, Kung Yao, Ralph E. Hudson, D. Korompis, Flavio Lorenzelli, S. Soli, S. Gao. 231-239 [doi]
- Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel SystemsDavid R. Surma, Edwin Hsing-Mean Sha. 240-249 [doi]
- Design of the Distributed Architecture of a Machine-tool Using FIP FieldbusDaping Song, Thierry Divoux, Francis Lepage. 250 [doi]
- NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit SynthesisKarl M. Fant, Scott A. Brandt. 261-273 [doi]
- A Synthesis System For Bus-Based Wavefront Array ArchitecturesReiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger. 274-283 [doi]
- Hardware Synthesis From Encapsulated Verilog ModulesDavid R. Smith. 284 [doi]
- Reconfigurable Processing With Field Programmable Gate ArraysBradly K. Fawcett, J. Watson. 293-302 [doi]
- Rapid Prototyping of Reconfigurable CoprocessorsNaren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri. 303-312 [doi]
- Performance Modeling and Tradeoff Analysis During Rapid PrototypingJeffrey Walrath. 313-322 [doi]
- Jacobi-Specific Processor ArraysHylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere. 323 [doi]
- A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task AllocationJames E. Beck, Daniel P. Siewiorek. 342-352 [doi]
- On the Removal of Anti and Output DependencesPierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien. 353-364 [doi]
- Latency-constrained Resynchronization for Multiprocessor DSP ImplementationShuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee. 365-380 [doi]
- Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence EquationsFlorent de Dinechin, Sophie Robert. 381 [doi]
- Extension Of The Alpha Language To Recurrences On Sparse Periodic DomainsPatrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset. 391-401 [doi]
- On Supernode Transformation with Minimized Total Running TimeEdin Hodzic, Weijia Shang. 402-414 [doi]
- Parametric Analysis of Polyhedral Iteration SpacesPhilippe Clauss, Vincent Loechner. 415 [doi]