Abstract is missing.
- Simulation-based functional test generation for embedded processorsCharles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng. 3-10 [doi]
- Scalable defect mapping and configuration of memory-based nanofabricsChen He, Margarida F. Jacome, Gustavo de Veciana. 11-18 [doi]
- Improvement of fault injection techniques based on VHDL code modificationJuan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil. 19-26 [doi]
- MVP: a mutation-based validation paradigmJorge Campos, Hussain Al-Asaad. 27-34 [doi]
- Establishing latch correspondence for embedded circuits of PowerPC microprocessorsHimyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis. 37-44 [doi]
- Sequential equivalence checking based on k-th invariants and circuit SAT solvingFeng Lu, Kwang-Ting (Tim) Cheng. 45-51 [doi]
- VERISEC: verifying equivalence of sequential circuits using SATManan Syal, Michael S. Hsiao. 52-59 [doi]
- Automated clock inference for stream function-based system level specificationsJean-Pierre Talpin, Sandeep Kumar Shukla. 63-70 [doi]
- Cosimulation of ITRON-based embedded software with SystemCShin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada. 71-76 [doi]
- A software test program generator for verifying system-on-chipsAdriel Cheng, Cheng-Chew Lim, Atanas N. Parashkevov. 79-86 [doi]
- Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine modelChe-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou. 87-93 [doi]
- DVGen: a test generator for the transmeta Efficeon VLIW processorKevin D. Rich, Shankar G. Govindaraju, Robert Shaw, David Dobrikin. 94-101 [doi]
- Reuse in system-level stimuli-generationYoav Katz, Itai Jaeger, Roy Emek, Yossi Lichtenstein, Anita Devadason, Audrey Romonosky. 105-111 [doi]
- Harnessing machine learning to improve the success rate of stimuli generationShai Fine, Ari Freund, Itai Jaeger, Yehuda Naveh, Avi Ziv, Yishay Mansour. 112-118 [doi]
- A new simulation-based property checking algorithm based on partitioned alternative search space traversalQingwei Wu, Michael S. Hsiao. 121-126 [doi]
- Validating families of latency insensitive protocolsSyed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner. 127-134 [doi]
- GASIM: a fast Galois field based simulator for functional modelDhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir. 135-142 [doi]
- Overlap reduction in symbolic system traversalPrakash Mohan Peranandam, Pradeep Kumar Nalla, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel. 145-152 [doi]
- Formal verification of high-level conformance with symbolic simulationRoope Kaivola, Armaghan Naik. 153-159 [doi]
- A method for generation of GSTE assertion graphsEdward Smith. 160-167 [doi]
- Automatic abstraction refinement for Petri nets verificationZhenyu Chen, Conghua Zhou, Decheng Ding. 168-174 [doi]
- An optimum algorithm for compacting error traces for efficient functional debuggingChia-Chih Yen, Jing-Yang Jou. 177-183 [doi]
- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checkingVishnu C. Vimjam, Michael S. Hsiao. 184-191 [doi]
- B-cubing theory: new possibilities for efficient SAT-solvingDomagoj Babic, Jesse D. Bingham, Alan J. Hu. 192-199 [doi]
- Multilevel design validation in a secure embedded systemDavid D. Hwang, Shenglin Yang, Ingrid Verbauwhede, Patrick Schaumont. 203-210 [doi]
- Security evaluation against electromagnetic analysis at design timeHuiyun Li, A. Theodore Markettos, Simon W. Moore. 211-218 [doi]
- Formal meaning of coverage metrics in simulation-based hardware design verificationIñigo Ugarte, Pablo Sanchez. 221-228 [doi]
- Advanced analysis techniques for cross-product coverageHezi Azatchi, Laurent Fournier, Avi Ziv, Keren Zohar. 229-236 [doi]
- A proof of correctness for the construction of property monitorsKatell Morin-Allory, Dominique Borrione. 237-244 [doi]
- Panel: Functional coverage - is your design exposed?Andrew Piziali, Avi Ziv. 247 [doi]