Abstract is missing.
- Optimization and Analysis Techniques for the Deep Submicron RegimeNoel Menezes, Sachin S. Sapatnekar. 3-4
- Embedded Memories in System Design: Technology, Application, Design and ToolsDoris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda. 5-6
- ntroduction to SystemCSudipta Bhawmik. 7-8
- Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design MethodologiesAnand Raghunathan, Sujit Dey. 9-10
- IBM s Blue Logic Design Methodology-Circuits and Physical DesignRuchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty. 11-12
- Next Generation Network ProcessorsDeepak Kataria. 13-15
- Functional Verification of Programmable DSP CoresMahesh Mehendale, Santhosh Kumar Amanna. 16-17
- Tutorial: CMOS Analog Circuits for Wireless CommunicationsRamesh Harjani, Jackson Harvey. 18
- System Level Testability Issues of Core Based System-on-a-ChipV. Ranganatha, R. Sunda. 18
- Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case StudyAnupam Rastogi, M. Balakrishnan, Anshul Kumar. 23-28 [doi]
- Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication ArchitecturesKanishka Lahiri, Sujit Dey, Anand Raghunathan. 29-35 [doi]
- Performance Considerations in Embedded DSP based System-On-a-Chip DesignsAjit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair. 36-41 [doi]
- Hardware Software Codesign of DSP System Using Grammar Based ApproachAbhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist. 42-47 [doi]
- A Systematic Approach for System Bus Load Reduction Applied to Medical ImagingKoen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari. 48 [doi]
- Battery Life Estimation of Mobile Embedded SystemsDebashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan. 57-63 [doi]
- Power-aware Multimedia Systems using Run-time PredictionPavan Kumar, Mani B. Srivastava. 64-69 [doi]
- Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description LanguagePrabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau. 70-75 [doi]
- ASIP Design Methodologies : Survey and IssuesManoj Kumar Jain, M. Balakrishnan, Anshul Kumar. 76 [doi]
- ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded ApplicationsG. Surendra, S. K. Nandy, Paul Sathya. 85-90 [doi]
- The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design ProcessesVineet Sahula, C. P. Ravikumar. 91-96 [doi]
- Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout TechniqueAnupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt. 97-102 [doi]
- Error Diagnosis of Sequential Circuits Using Region-Based ModeAnand L. D Souza, Michael S. Hsiao. 103 [doi]
- On Improving Static Test Compaction for Sequential CircuitsRuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy. 111-116 [doi]
- On Fault-Simulation Through Embedded Memories On Large Industrial DesignsSitaram Yadavalli, Sandip Kundu. 117-121 [doi]
- A Novel Strategy to Test Core Based DesignsDebabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay. 122-127 [doi]
- Testable Design of Sequential Circuits with Improved Fault EfficiencyDebesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara. 128-133 [doi]
- Combination of Structural and State Analysis for Partial ScanSameer Sharma, Michael S. Hsiao. 134 [doi]
- Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG ModelYong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal. 143-148 [doi]
- Synthesis of System-on-a-chip for TestabilitySrivaths Ravi, Niraj K. Jha. 149-156 [doi]
- Timing Verification and Delay Test Generation for Hierarchical DesignsArun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri. 157-162 [doi]
- A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy IdentificationJian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel. 163 [doi]
- Implementation of Read- k-times BDDs on Top of Standard BDD PackagesWolfgang Günther, Rolf Drechsler. 173-178 [doi]
- Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory ModelSiddharth R. Phanse, R. K. Shyamasundar. 179-188 [doi]
- Design Verification and Functional Testing of FiniteState MachinesMark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr. 189-195 [doi]
- Design Of Provably Correct Storage ArraysRajiv V. Joshi, Wei Hwang, Andreas Kuehlmann. 196 [doi]
- Low-Power Wireless Sensor NetworksRex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha Chandrakasan. 205-210 [doi]
- Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital LogicHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul. 211-214 [doi]
- Average Power in Digital CMOS Circuits using Least Square EstimationAshok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali. 215-220 [doi]
- Dynamic Voltage Scheduling Using Adaptive Filtering of Workload TracesAmit Sinha, Anantha Chandrakasan. 221-226 [doi]
- Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS CircuitsNikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal. 227 [doi]
- Accurate Power Macro-modeling Techniques for Complex RTL CircuitsNachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar. 235-241 [doi]
- Architecture of Reconfigurable a Low Power Gigabit AT SwitchAbhijit M. Lele, S. K. Nandy. 242-247 [doi]
- Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution NetworksDavid Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. 248-253 [doi]
- Software Power Optimizations In An Embedded SystemVishal Dalal, C. P. Ravikumar. 254 [doi]
- Library Binding for High-Level Synthesis of Analog SystemsSree Ganesan, Ranga Vemuri. 261-268 [doi]
- An Integrated Quadrature Mixer with Improved Image Rejection at Low VoltageJackson Harvey, Ramesh Harjani. 269-273 [doi]
- A Code Transition Delay Model for ADC TestSanjay Mohan, Michael L. Bushnell. 274-282 [doi]
- Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting MatricesAlper Demir, David E. Long, Jaijeet S. Roychowdhury. 283 [doi]
- Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic BlocksK. Yan. 291-298 [doi]
- Fpga Hardware Synthesis From MatlabMalay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, U. Nagaraj Shenoy. 299-304 [doi]
- Efficient Synthesis of Array Intensive Computations onto FPGA Based AcceleratorsU. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir. 305-310 [doi]
- Performance Driven Optimization for MUX based FPGAsWolfgang Günther, Rolf Drechsler. 311-316 [doi]
- Application Specific Macro Based SynthesisSujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri. 317 [doi]
- Modeling of Nonuniform Interconnects by Using Differential Quadrature MethodQinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya. 327-332 [doi]
- A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI CircuitsSujit T. Zachariah, Sreejit Chakravarty. 333-338 [doi]
- How to Half Wire Lengths in the Layout of Cyclic ShifterMark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel. 339-344 [doi]
- Partitioning Routing Area into Zones with Distinct PinsKoushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta. 345 [doi]
- Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing StrategiesSabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami. 353-358 [doi]
- Transmission Line Modeling by Modified Method of CharacteristicsQinwei Xu, Pinaki Mazumder, Zheng-Fan Li. 359-364 [doi]
- Crosstalk Noise Verification in Digital Designs with Interconnect Process VariationsNagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell. 365-370 [doi]
- Early Evaluation Of Bus Interconnects Dependability For System-On-Chip DesignsMarcello Lajolo, Matteo Sonza Reorda, Massimo Violante. 371 [doi]
- An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory BuffersDer-Cheng Huang, Wen-Ben Jone, Sunil R. Das. 379-384 [doi]
- Observability Register Architecture For Efficient Production Test And Debug Of Vlsi CircuitsDilip K. Bhavsar, Rishan Tan. 385-390 [doi]
- Efficient Signature-Based Fault Diagnosis Using Variable Size WindowsThomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi. 391-396 [doi]
- A Parallel Built-In Self-Diagnostic Method For Embedded Memory BuffersDer-Cheng Huang, Wen-Ben Jone, Sunil R. Das. 397-402 [doi]
- Hierarchical Cellular Automata As An On-Chip Test Pattern GeneratorBiplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly. 403 [doi]
- High Level Synthesis Of Multi-Precision Data Flow GraphsVikas Agrawal, Anand Pande, Mahesh Mehendale. 411-416 [doi]
- Multilevel Logic Minimization Using Functional Don t CaresL. Wang, A. E. A. Almaini. 417-424 [doi]
- Complexity Of Minimum-Delay Gate ResizingSupratik Chakraborty, Rajeev Murgai. 425-430 [doi]
- Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip TestKrishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee. 431 [doi]
- Scaling Up Of Wave PipelinesMasa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura. 439-445 [doi]
- Vlsi Architectures For High-Speed Map DecodersAlexander Worm, Holger Lamm, Norbert Wehn. 446-453 [doi]
- Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi CircuitsBiplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly. 454-459 [doi]
- Synthesizing A Long Latency Unit Within Vliw ProcessorRam Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa. 460 [doi]
- Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit PerformanceOmkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler. 469-469
- Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic GatesMayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax. 470-474 [doi]
- erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel EngineeringG. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele. 475-478 [doi]
- Effect Of Fringing Capacitances In Sub 100 Nm Mosfet s With High-K Gate DielectricsNihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao. 479 [doi]
- Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain JunctionsR. K. Jarwal, Durga Misra. 485-490 [doi]
- High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos TransistorsB. Prasad, P. J. George, Chandra Shekhar. 491-494 [doi]
- An On-Chip Coupling Capacitance Measurement TechniquePratheep A. Nair, Anubhav Gupta, Madhav P. Desai. 495-499 [doi]
- Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc MultiportsShabbir H. Batterywala, H. Narayanan. 500 [doi]
- Repeater Insertion To Minimise Delay In Coupled InterconnectsDinesh Pamunuwa, Hannu Tenhunen. 513-517 [doi]
- Integrated Crosstalk And Oxide Integrity Analysis In Dsm DesignsN. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das. 518-523 [doi]
- Switching Noise Analysis Framework For High Speed Logic FamiliesMarco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. 524-530 [doi]
- Estimating Crosstalk From Vlsi LayoutsV. Sankara Subramanian, C. P. Ravikumar. 531 [doi]