A. E. A. Almaini - researchr alias

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Viewing Publication 1 - 19 from 19

2014

An Architecture Independent Packing Method for LUT-based Commercial FPGAMeng Yang, Jinmei Lai, A. E. A. Almaini. jcp, 9(5):1131-1137, 2014. [doi]

2013

Indirect connection aware attraction for FPGA clustering (abstract only)Meng Yang, Jiarong Tong, A. E. A. Almaini. fpga 2013: 265 [doi]

2011

State assignment for sequential circuits using multi-objective genetic algorithmB. A. Al Jassani, N. Urquhart, A. E. A. Almaini. iet-cdt, 5(4):296-305, 2011. [doi]

Reed-Muller function optimization techniques with onset tableLun-Yao Wang, Yinshui Xia, Xiexiong Chen, A. E. A. Almaini. jzusc, 12(4):288-296, 2011. [doi]

2010

Manipulation and optimisation techniques for Boolean logicB. A. Al Jassani, N. Urquhart, A. E. A. Almaini. iet-cdt, 4(3):227-239, 2010. [doi]

2008

Techniques for dual forms of Reed-Muller expansion conversionM. Yang, L. Wang, J. R. Tong, A. E. A. Almaini. integration, 41(1):113-122, 2008. [doi]

2006

Fast Conversion for Large Canonical OR-Coincidence FunctionsM. Yang, L. Wang, A. E. A. Almaini. apccas 2006: 1643-1646 [doi]

2005

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued ClockYinshui Xia, Lun-Yao Wang, A. E. A. Almaini. jcst, 20(2):237-242, 2005. [doi]

2004

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic CircuitsB. Ali, A. E. A. Almaini, Tatiana Kalganova. gpem, 5(1):11-29, 2004. [doi]

2003

The Application of the Wavelet Transform to Polysomnographic SignalsM. MacCallum, A. E. A. Almaini. ijwmip, 1(3):263-274, 2003. [doi]

Area and power optimization of FPRM function based circuitsYinshui Xia, B. Ali, A. E. A. Almaini. iscas 2003: 329-332 [doi]

Power Minimization of FPRM Functions Based on Polarity ConversionYinshui Xia, Xunwei Wu, A. E. A. Almaini. jcst, 18(3):325-331, 2003. [doi]

2002

Best Polarity for Low Power XOR Gate DecompositionYinshui Xia, A. E. A. Almaini. dsdm 2002: 53-59 [doi]

2001

The Application of the Wavelet Transform to Polysomnographic SignalsM. MacCallum, A. E. A. Almaini. waa 2001: 284-295 [doi]

Multilevel Logic Minimization Using Functional Don t CaresL. Wang, A. E. A. Almaini. vlsid 2001: 417-424 [doi]

1994

A Parallel CMOS 2 s Complement Multiplier Based on 5: 3 CounterZ. Guan, P. Thomson, A. E. A. Almaini. iccd 1994: 298-301

1990

An introduction to microcomputer systems architecture and interfacing: Fulcher, J Addison-Wesley, Workingham, UK (1989) pp 425A. E. A. Almaini. mam, 14(9):615, 1990. [doi]

ASIC implementation of a programmable error-trapping decoder for binary codes of length 15A. E. A. Almaini, S. S. Aziz. mam, 14(4):256-262, 1990. [doi]

1978

Sequential Machine Implementations Using Universal Logic ModulesA. E. A. Almaini. TC, 27(10):951-960, 1978.

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