Table of Contents

• Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC DevelopmentUlf Schlichtmann. 2-3 [doi]
• An Asynchronous Victim CacheDaranee Hormdee, Jim D. Garside, Stephen B. Furber. 4-11 [doi]
• Formal Verification of a DSP Chip Using an Iterative ApproachAli Habibi, Sofiène Tahar, Adel Ghazel. 12-19 [doi]
• Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual MachineKenneth B. Kent, Micaela Serra. 20-27 [doi]
• Enhanced Configurable Parallel Memory ArchitectureJarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen. 28-37 [doi]
• Recursive Bi-Partitioning of Netlists for Large Number of PartitionsRolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst. 38-44 [doi]
• Folded Bit-Plane FIR Filter Architecture with Changeable Folding FactorIvan Milentijevic, Vladimir Ciric, Teufik Tokic, Oliver Vojinovic. 45-52 [doi]
• Best Polarity for Low Power XOR Gate DecompositionYinshui Xia, A. E. A. Almaini. 53-59 [doi]
• A Hybrid Evolutionary Algorithm for Multi-FPGA Systems DesignJosé Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida. 60-69 [doi]
• A Flexible Architecture for H.263 Video CodingMatías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses. 70-77 [doi]
• The Synthesis of a Hardware Scheduler for Non-Manifest LoopsOmar Mansour, Egbert Molenkamp, Thijs Krol. 78-85 [doi]
• Configurable Memory Organisation for Communication ApplicationsJuha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen. 86-93 [doi]
• Enhanced Reusability for SoC-Based HW/SW Co-DesignMaik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke. 94-101 [doi]
• Integrating a Computational Model and a Run Time System for Image Processing on a UAVPer Andersson, Krzysztof Kuchcinski, Klas Nordberg, Patrick Doherty. 102-109 [doi]
• Specification and Simulation of Microprocessor Operations and Parallel InstructionsLoe M. G. Feijs, Paul Gorissen, Joachim Trescher. 110-117 [doi]
• Rapid Prototyping of Mixed Hardware and Software SystemsMartyn Edwards, Benjamin Fozard. 118-125 [doi]
• Integration of Instruction Set Simulators into SystemC High Level ModelsIlia Oussorov, Wolfgang Raab, J. A. Ulrich Hachmann, Alex Kravtsov. 126-131 [doi]
• Architecture Design of a Scalable Single-Chip Multi-ProcessorBart D. Theelen, A. C. Verschueren. 132-139 [doi]
• Parallel Multimedia Processor Using Customised Infineon TriCoresAri Wahyudi, Amos Omondi. 140-147 [doi]
• Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo BranchesManuel Lois Anido, Alexander Paar, Nader Bagherzadeh. 148-155 [doi]
• Implementation of a Streaming Execution UnitDmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff. 156-165 [doi]
• Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT LevelJosef Strnadel, Zdenek Kotásek. 166-173 [doi]
• Fault Latencies of Concurrent Checking FSMsRoman Goot, Ilya Levin, Sergei Ostanin. 174-179 [doi]
• Using Formal Tools to Study Complex Circuits BehaviourPaul Amblard, Fabienne Lagnier, Michel Lévy. 180-186 [doi]
• Integrated Design and Test Generation Under Internet Based Environment MOSCITOAndré Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng. 187-195 [doi]
• Networks on Silicon: Blessing or Nightmare?Paul Wielage, Kees G. W. Goossens. 196-200 [doi]
• Embedded Software: How To Make It Efficient?Peter Marwedel. 201-209 [doi]
• A Design for a Low-Power Digital Matched Filter Applicable to W-CDMAShoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura. 210-217 [doi]
• Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar MicroprocessorD. Piso, José-Alejandro Piñeiro, Javier D. Bruguera. 218-225 [doi]
• Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary ExponentiationNadia Nedjah, Luiza de Macedo Mourelle. 226-235 [doi]
• Decision Diagram Optimization Using Copy PropertiesDragan Jankovic, Radomir S. Stankovic, Rolf Drechsler. 236-243 [doi]
• Use of the Autocorrelation Function in the Classification of Switching FunctionsJacqueline E. Rice, Jon C. Muzio. 244-251 [doi]
• Optimization of Equational Specifications Using Genetic TechniquesAitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida. 252-258 [doi]
• Synthesis of Multipurpose Reversible Logic GatesPawel Kerntopf. 259-267 [doi]
• Performance of Remote FPGA-Based Coprocessors for Image-Processing ApplicationsDomingo Benitez. 268-275 [doi]
• Improving mW/MHz Ratio in FPGAs Pipelined DesignsOswaldo Cadenas, Graham M. Megson. 276-282 [doi]
• Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot NavigationM. A. Hannan Bin Azhar, Keith R. Dimond. 283-290 [doi]
• Constant Coefficient Convolution Implemented in FPGAsErnest Jamro, Kazimierz Wiatr. 291-298 [doi]
• An Evaluation of an FPGA Run-Time Support SystemPeter Green, M. Vakondios, Martyn Edwards. 299-307 [doi]
• Efficient Verification of Scheduling, Allocation and Binding in High-Level SynthesisJosé M. Mendías, Román Hermida, María C. Molina, Olga Peñalba. 308-315 [doi]
• An Efficient List-Based Scheduling Algorithm for High-Level SynthesisAzeddien M. Sllame, Vladimír Drábek. 316-323 [doi]
• Source Code Transformation to Improve Conditional Hardware ReuseOlga Peñalba, José M. Mendías, Román Hermida. 324-331 [doi]
• Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 TransducersZeljko Vujovic. 332-336 [doi]
• Reachability Analysis for Formal Verification of SystemCRolf Drechsler, Daniel Große. 337-340 [doi]
• Simplifying Instruction Issue Logic in Superscalar ProcessorsToshinori Sato, Itsujiro Arita. 341-346 [doi]
• A Self-Timed Arithmetic Unit for Elliptic Curve CryptographyMartin Feldhofer, Thomas Trathnigg, Bernd Schnitzer. 347-350 [doi]
• Low Power Strategy for a TFT ControllerGiuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo 0002, Agatino Pennisi, Gaetano Palumbo. 351-354 [doi]
• Hardware Implementation of a Memory AllocatorKhushwinder Jasrotia, Jianwen Zhu. 355-358 [doi]
• Evolutionary Algorithm for State Assignment of Finite State MachinesMariusz Chyzy, Witold Kosinski. 359-363 [doi]
• Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement AnalysisRonny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig. 364-370 [doi]
• On the Fundamental Design Gap in Terabit per Second Packet SwitchingM. Verhappen, P. H. A. van der Putten, Jeroen Voeten. 371-379 [doi]
• Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for IntegersRajendra S. Katti. 380-384 [doi]
• Bit-Level Allocation of Multiple-Precision SpecificationsMaría C. Molina, José M. Mendías, Román Hermida. 385-392 [doi]