Nihar R. Mohapatra - researchr alias

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Viewing Publication 1 - 10 from 10

2019

Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical ApplicationsYadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra. vdat 2019: 590-604 [doi]

2018

An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS TechnologyTanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly. drc 2018: 1-2 [doi]

2017

Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact modelApoorva Ojha, Nihar R. Mohapatra. essderc 2017: 200-203 [doi]

Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETsAshish Soni, Abhijit Umap, Nihar R. Mohapatra. vdat 2017: 227-238 [doi]

2016

Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel arrayHari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, D. K. Sharma. isqed 2016: 462-467 [doi]

Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS TransistorsApoorva Ojha, Narendra Parihar, Nihar R. Mohapatra. vlsid 2016: 323-327 [doi]

2003

Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuitsD. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao. vlsid 2003: 128 [doi]

Detailed Analysis of FIBL in MOS Transistors with High-K Gate DielectricsNihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao. vlsid 2003: 99-104 [doi]

2001

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet s With High-K Gate DielectricsNihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao. vlsid 2001: 479 [doi]

Sub-100 nm CMOS circuit performance with high-K gate dielectricsNihar R. Mohapatra, A. Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao. mr, 41(7):1045-1048, 2001. [doi]

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