Table of Contents

• WelcomeBrian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, Ali Iranmanesh. [doi]
• Sizing-priority based low-power embedded memory for mobile video applicationsSeyed Alireza Pourbakhsh, Xiaowei Chen, Dongliang Chen, Xin Wang, Na Gong, Jinhui Wang. 1-5 [doi]
• Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysisNavid Khoshavi, Xunchao Chen, Jun Wang, Ronald F. DeMara. 6-11 [doi]
• Optimizing SRAM bitcell reliability and energy for IoT applicationsHarsh N. Patel, Farah B. Yahya, Benton H. Calhoun. 12-17 [doi]
• Variability- and correlation-aware logical effort for near-threshold circuit designJun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 18-23 [doi]
• Design challenges and methodologies in 3D integration for neuromorphic computing systemsM. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi. 24-28 [doi]
• Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICsSheng-En David Lin, Partha Pratim Pande, Dae-Hyun Kim. 29-34 [doi]
• Electromigration-aware placement for 3D-ICsTiantao Lu, Zhiyuan Yang, Ankur Srivastava. 35-40 [doi]
• Monolithic 3D IC design: Power, performance, and area impact at 7nmKartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim. 41-48 [doi]
• Maximizing the performance of NoC-based MPSoCs under total power and power density constraintsAlireza Shafaei, Yanzhi Wang, Lizhong Chen, Shuang Chen, Massoud Pedram. 49-56 [doi]
• Process variation aware crosstalk mitigation for DWDM based photonic NoC architecturesSai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha. 57-62 [doi]
• Memory-aware circuit overlay NoCs for latency optimized GPGPU architecturesVenkata Yaswanth Raparti, Sudeep Pasricha. 63-68 [doi]
• Design guidelines for embeded NoCs on FPGAsNoha Gamal, Hossam A. H. Fahmy, Yehea I. Ismail, Hassan Mostafa. 69-74 [doi]
• A delay variation and floorplan aware high-level synthesis algorithm with body biasingKoki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa. 75-80 [doi]
• Exploring the use of volatile STT-RAM for energy efficient video processingHengyu Zhao, Hongbin Sun, Qiang Yang, Tai Min, Nanning Zheng. 81-87 [doi]
• Low power data-aware STT-RAM based hybrid cache architectureMohsen Imani, Shruti Patil, Tajana S. Rosing. 88-94 [doi]
• Yield estimation and statistical design of memristor cross-point memory systemsJizhe Zhang, Sandeep K. Gupta. 95-100 [doi]
• ReMAM: Low energy Resistive Multi-stage Associative Memory for energy efficient computingMohsen Imani, Pietro Mercati, Tajana Rosing. 101-106 [doi]
• Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applicationsNavneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. 107-112 [doi]
• Sparsely connected neural networks in FPGA for handwritten digit recognitionLuca Bochi Saldanha, Christophe Bobda. 113-117 [doi]
• Neuromorphic architectures with electronic synapsesSukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong. 118-123 [doi]
• Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithmsDan Christiani, Cory E. Merkel, Dhireesha Kudithipudi. 124-128 [doi]
• Equivalence checking between SLM and RTL using machine learning techniquesJian Hu, Tun Li, Sikun Li. 129-134 [doi]
• Very low supply voltage room temperature test to screen low temperature soft blown fuse fails which result in a resistive bridgePeter Sarson. 135-139 [doi]
• On-line harmonic-aware partitioned scheduling for real-time multi-core systems under RMSMing Fan, Rong Rong, Xinwei Niu. 140-145 [doi]
• Covgen: A framework for automatic extraction of functional coverage modelsEman El Mandouh, Amr G. Wassal. 146-151 [doi]
• In-situ Trojan authentication for invalidating hardware-Trojan functionsMasaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa. 152-157 [doi]
• A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applicationsAbhishek Roy, Peter J. Grossmann, Steven A. Vitale, Benton H. Calhoun. 158-162 [doi]
• Statistical quality modeling of approximate hardwareSeogoo Lee, Dongwook Lee, Kyungtae Han, Emily Shriver, Lizy K. John, Andreas Gerstlauer. 163-168 [doi]
• Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodesMeng-Yen Wu, Meng-Hsueh Chiang. 169-172 [doi]
• Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural networkLang Zhang, Hai Wang, Sheldon X.-D. Tan. 173-178 [doi]
• Detection of malicious hardware components in mobile platformsFatih Karabacak, Ïmit Y. Ogras, Sule Ozev. 179-184 [doi]
• An effective BIST architecture for power-gating mechanisms in low-power SRAMsAlberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan. 185-191 [doi]
• Performance evaluation considering mask misalignment in multiple patterning decompositionHaitong Tian, Martin D. F. Wong. 192-197 [doi]
• UM-BUS: An online fault-tolerant bus for embedded systemsJiqin Zhou, Weigong Zhang, Keni Qiu, Xiaoyan Zhu. 198-204 [doi]
• Low-leakage and process-variation-tolerant write-read disturb-free 9T SRA cell using CMOS and FinFETsAyushparth Sharma, Kusum Lata. 205-210 [doi]
• Ruggedness evaluation and design improvement of automotive power MOSFETsTianhong Ye, Kuan W. A. Chee. 211-214 [doi]
• Device/system performance modeling of stacked lateral NWFET logicVictor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi. 215-220 [doi]
• Accelerating physical level sub-component power simulation by online power partitioningSiddharth S. Bhargav, Andrew Kolb, Young H. Cho. 221-226 [doi]
• Power efficient router architecture for wireless Network-on-ChipHemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore, Shashwat Kaushik, Sujay Deb. 227-233 [doi]
• Preventing integrated circuit piracy via custom encoding of hardware instruction setVinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu. 234-241 [doi]
• Preventing design reverse engineering with reconfigurable spin transfer torque LUT gatesTheodore Winograd, Hassan Salmani, Hamid Mahmoodi, Houman Homayoun. 242-247 [doi]
• Portable biosensor for chronic malaria detectionLalitha Sivaraj, Nurul Amziah Md Yunus, Mohd Nazim Mokhtar, Samsuzana Abd Aziz, Zurina Zainal Abidin, M. Iqbal Saripan, Fakhrul Zaman Rokhani. 248-251 [doi]
• Performance modeling and optimization for on-chip interconnects in 3D memory arraysJavaneh Mohseni, Chenyun Pan, Azad Naeemi. 252-257 [doi]
• Near-threshold circuit variability in 14nm FinFETs for ultra-low power applicationsSriram Balasubramanian, Ninad Pimparkar, Mangesh Kushare, Vinayak Mahajan, Juhi Bansal, Takashi Shimizu, Vivek Joshi, Kun Qian, Arunima Dasgupta, Karthik Chandrasekaran, Chad Weintraub, Ali Icel. 258-262 [doi]
• An efficient timing analysis model for 6T FinFET SRAM using current-based methodTiansong Cui, Ji Li, Alireza Shafaei, Shahin Nazarian, Massoud Pedram. 263-268 [doi]
• Nanowire transistor solutions for 5nm and beyondA. Asenov, Yangang Wang, B. Cheng, Xingsheng Wang, Plamen Asenov, T. Al-Ameri, Vihar P. Georgiev. 269-274 [doi]
• 5nm: Has the time for a device change come?Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean. 275-277 [doi]
• Transistor design for 5nm and beyond: Slowing down electrons to speed up transistorsVictor Moroz, Joanne Huang, Reza Arghavani. 278-283 [doi]
• Decomposition technologies for advanced nodesFedor G. Pikus. 284-288 [doi]
• Low capture power dictionary-based test data compressionPanagiotis Sismanoglou, Dimitris Nikolos. 289-294 [doi]
• Analysis of setup and hold margins inside silicon for advanced technology nodesDeepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio. 295-300 [doi]
• Protocol-guided analysis of post-silicon traces under limited observabilityHao Zheng, Yuting Cao, Sandip Ray, Jin Yang. 301-306 [doi]
• Nonlinear delay-table approach for full-chip NBTI degradation predictionSong Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato. 307-312 [doi]
• Reliability and energy-aware cache reconfiguration for embedded systemsYuanwen Huang, Prabhat Mishra. 313-318 [doi]
• Architecting STT Last-Level-Cache for performance and energy improvementFazal Hameed, Mehdi Baradaran Tahoori. 319-324 [doi]
• Instruction cache aging mitigation through Instruction Set EncodingAnteneh Gebregiorgis, Fabian Oboril, Mehdi Baradaran Tahoori, Said Hamdioui. 325-330 [doi]
• Harvesting-aware adaptive energy management in solar-powered embedded systemsNga Dang, Zana Ghaderi, Moonju Park, Eli Bozorgzadeh. 331-337 [doi]
• Negotiation-based resource provisioning and task scheduling algorithm for cloud systemsJi Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram. 338-343 [doi]
• Digital IP protection using threshold voltage controlJoseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula. 344-349 [doi]
• Trojan detection in digital systems using current sensing of pulse propagation in logic gatesSabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee. 350-355 [doi]
• Active protection against PCB physical tamperingSteven Paley, Tamzidul Hoque, Swarup Bhunia. 356-361 [doi]
• SVM-based real-time hardware Trojan detection for many-core platformAmey M. Kulkarni, Youngok Pino, Tinoosh Mohsenin. 362-367 [doi]
• On testing physically unclonable functions for uniquenessArunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu. 368-373 [doi]
• Dot-product engine as computing memory to accelerate machine learning algorithmsMiao Hu, John Paul Strachan, Zhiyong Li, R. Stanley Williams. 374-379 [doi]
• 0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy busKhaja Ahmad Shaik, Kiyoo Itoh, Amara Amara. 380-385 [doi]
• Analysis and design of a triangular active charge injection for stabilizing resonant power supply noiseMasahiro Kano, Toru Nakura, Kunihiro Asada. 386-391 [doi]
• An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithmZheyu Liu, Fei Qiao, Qi Wei, Xinghua Yang, Yi Li, Huazhong Yang. 392-397 [doi]
• Impact of interconnect variability on circuit performance in advanced technology nodesDivya Prasad, Chenyun Pan, Azad Naeemi. 398-404 [doi]
• Hotspot detection using machine learningKareem Madkour, Sarah Mohamed, Dina Tantawy, Mohab Anis. 405-409 [doi]
• Efficient analog circuit optimization using sparse regression and error marginingMohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi. 410-415 [doi]
• State encoding based NBTI optimization in finite state machinesShilpa Pendyala, Srinivas Katkoori. 416-422 [doi]
• Gate movement for timing improvement on row based Dual-VDD designsHua Xiang, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu. 423-429 [doi]
• Multiple shift-vector importance sampling method using support vector machine and clustering for high-density DRAM designsJinyoung Lee, Sunghee Yun, Jeongha Kim, Dongsoo Kang, Jeongyeol Kim, Sanghoon Lee. 430-436 [doi]
• Fully automated PLL compiler generating final GDS from specificationToru Nakura, Kunihiro Asada. 437-442 [doi]
• AFD-based method for signal line EM reliability evaluationZhong Guan, Malgorzata Marek-Sadowska. 443-449 [doi]
• A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devicesShuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu. 450-455 [doi]
• Making unreliable Chem-FET sensors smart via soft calibrationFatih Karabacak, Uwadiae Obahiagbon, Ümit Ogras, Sule Ozev, Jennifer Blain Christen. 456-461 [doi]
• Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel arrayHari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, D. K. Sharma. 462-467 [doi]
• Time-division multiple access based intra-body communication for wearable health trackerTan Chee Phang, Mohammad Harris Mokhtar, Mohd Nazim Mokhtar, Fakhrul Zaman Rokhani. 468-472 [doi]