Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs

Sheng-En David Lin, Partha Pratim Pande, Dae-Hyun Kim. Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs. In 17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016. pages 29-34, IEEE, 2016. [doi]

Abstract

Abstract is missing.