Table of Contents

• Automations and Methodologies for Efficient and Quality Conscious Analog Layout ImplementationVarun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu. 3-13 [doi]
• A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power AmplifierArchana Sunitha, Bhaskar Manickam. 14-22 [doi]
• A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes ApplicationJaved S. Gaggatur, Abhishek Chaturvedi. 23-35 [doi]
• Analyzing Design Parameters of Nano-Magnetic Technology Based Converter CircuitBandan Kumar Bhoi, Neeraj Kumar Misa, Shailesh Singh Chouhan, Sarthak Acharya. 36-46 [doi]
• Design of Current Mode Sigmoid Function and Hyperbolic Tangent FunctionDebanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj, Baidyanath Ray, Ayan Banerjee. 47-60 [doi]
• Flexible Adaptive FIR Filter Designs Using LMS AlgorithmM. Mohamed Asan Basiri. 61-71 [doi]
• An Efficient Test and Fault Tolerance Technique for Paper-Based DMFBChandan Das, Sarit Chakraborty, Susanta Chakraborty. 72-86 [doi]
• A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design MethodologyAmartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal. 87-101 [doi]
• A Space Efficient Greedy Droplet Routing for Digital Microfluidics BiochipJyotiranjan Swain, Rajesh Kolluri, Sumanta Pyne. 102-114 [doi]
• Design of 635 MHz Bandpass Filter Using High-Q Floating Active InductorAditya Kumar Hota, Kabiraj Sethi. 115-125 [doi]
• Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS TechnologySaroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer. 126-140 [doi]
• Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADCM. Mahendra Reddy, Sounak Roy. 141-149 [doi]
• Approximate Computing Based Adder Design for DWT ApplicationMoumita Acharya, Samik Basu 0003, Biranchi Narayan Behera, Amlan Chakrabarti. 150-163 [doi]
• An Efficient Wireless Charging Technique Using Inductive and Resonant CircuitsPurvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder. 164-170 [doi]
• A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron TechnologySwatilekha Majumdar. 171-179 [doi]
• On-Chip Threshold Compensated Voltage Doubler for RF Energy HarvestingArun Mohan, Saroj Mondal, Surya Shankar Dan. 180-189 [doi]
• Utilizing NBTI for Operation Detection of Integrated CircuitsAmbika Prasad Shah, Amirhossein Moshrefi, Michael Waltl. 190-201 [doi]
• A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOSRaviteja Kammari, Vijaya Sankara Rao Pasupureddi. 202-214 [doi]
• A CMOS Low Noise Amplifier with Improved GainSunanda Ambulker, Jitendra Kumar Mishra, Sangeeta Nakhate. 215-223 [doi]
• Radiation Hardened by Design Sense AmplifierAvinash Verma, Gaurav Kaushal. 224-235 [doi]
• Delay Efficient All Optical Carry Lookahead AdderSayantani Roy, Arighna Deb, Debesh K. Das. 236-244 [doi]
• Asynchronous Hardware Design for Floating Point Multiply-Accumulate CircuitM. Mohamed Asan Basiri. 247-257 [doi]
• A Unified Methodology for Hardware Obfuscation and IP WatermarkingSaurabh Gangurde, Binod Kumar. 258-271 [doi]
• Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack ResistanceS. Shanthi Rekha, P. Saravanan. 272-285 [doi]
• Brain Inspired One Shot Learning Method for HD ComputingDevika R. Nair, A. Purushothaman. 286-297 [doi]
• Dual-Edge Triggered Lightweight Implementation of AES for IoT SecuritySajid Khan, Neha Gupta, Abhinav Vishvakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma. 298-307 [doi]
• 2L-2D Routing for Buffered Mesh Network-on-ChipRose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose. 308-320 [doi]
• Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural NetworkGopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma. 321-333 [doi]
• An Ultra Low Power AES Architecture for IoTSajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma. 334-344 [doi]
• Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 ProcessorRajul Bansal, Abhijit Karmakar. 345-356 [doi]
• Investigating the Role of Parasitic Resistance in a Class of Nanoscale InterconnectsShah Zahid Yousuf, Anil Kumar Bhardwaj, Rohit Sharma. 357-370 [doi]
• A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold DesignsPriyamvada Sharma, Bishnu Prasad Das. 371-382 [doi]
• ASIC Based LVDT Signal Conditioner for High-Accuracy MeasurementsK. P. Raghunath, K. V. Manu Sagar, T. Gokulan, Kundan Kumar, Chetan Singh Thakur. 385-397 [doi]
• Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC StandardNeelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma 0001. 398-412 [doi]
• Identification of Effective Guidance Hints for Better Design Debugging by Formal MethodsV. S. Vineesh, Binod Kumar, Jay Adhaduk. 413-427 [doi]
• Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching MechanismsPiyush Tankwal, Vikas Nehra, Brajesh Kumar Kaushik. 428-441 [doi]
• Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable ArchitectureP. Veda Bhanu, Pranav Venkatesh Kulkarni, Sai Pranavi Avadhanam, Soumya J., Linga Reddy Cenkeramaddi. 442-454 [doi]
• A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular AutomataMrinal Goswami, Mayukh Roy Choudhury, Bibhash Sen. 455-467 [doi]
• User Guided Register Manipulation in Digital CircuitsPriyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa. 468-481 [doi]
• RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processorAneesh Raveendran, Sandra Jean, J. Mervin, D. Vivian, A. David Selvakumar. 482-495 [doi]
• Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPUAneesh Raveendran, Vinay Kumar, D. Vivian, David Selvakumar. 496-509 [doi]
• Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of ThingsGovind Bajpai, Aniket Gupta, Nitanshu Chauhan. 510-522 [doi]
• A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved PerformanceAnushka Singh, Yash Sharma, Arvind Sharma, Archana Pandey. 523-531 [doi]
• Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-FlopMuneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Tripathi. 532-540 [doi]
• Design and Analysis for Power Reduction with High SNM of 10T SRAM CellKamini Singh, R. S. Gamad, P. P. Bansod. 541-549 [doi]
• A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF ApplicationsKanika Monga, Nitin Chaturvedi. 553-564 [doi]
• Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression ModelsDeepthi Amuru, Andleeb Zahra, Zia Abbas. 565-578 [doi]
• A Novel Design of SRAM Using Memristors at 45 nm TechnologyV. Jeffry Louis, Jai Gopal Pandey. 579-589 [doi]
• Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical ApplicationsYadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra. 590-604 [doi]
• An Approach for Detection of Node Displacement Fault (NDF) in Reversible CircuitBappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, Hafizur Rahaman. 605-616 [doi]
• Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR InterconnectsVijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder. 617-629 [doi]
• A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM CellNeha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma. 630-642 [doi]
• Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM CellNeha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma. 643-654 [doi]
• Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power ApplicationsAnkur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma. 655-663 [doi]
• Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK ModelShivendra Singh Parihar, Ramchandra Gurjar. 667-678 [doi]
• Technology Characterization Model and Scaling for Energy ManagementHarshil Goyal, Vishwani D. Agrawal. 679-693 [doi]
• GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FETShivendra Yadav, Chithraja Rajan, Dheeraj Sharma, Sanjay Balotiya. 694-701 [doi]
• Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core ArchitecturesNirmal Kumar Boran, Dinesh Kumar Yadav, Rishabh Iyer. 702-715 [doi]
• Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain UnderlapVenkata Appa Rao Yempada, Srivatsava Jandhyala. 716-726 [doi]
• Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and DrainShagun Pal, Brijesh Kumar. 727-738 [doi]
• A Latency and Throughput Efficient Successive Cancellation Decoding of Polar CodesSistla Lakshmi Manasa, G. Lakshmi Narayanan. 741-748 [doi]
• All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical ModelAnkur Pokhara, Biswajit Mishra, Purvi Patel. 749-763 [doi]
• Intelligent Traffic Light Controller: A Solution for Smart City Traffic ProblemAnam Sabir, Anushree Jain, Yashwini Nathwani, Vaibhav Neema. 764-772 [doi]