Venkata Appa Rao Yempada, Srivatsava Jandhyala. Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap. In Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma, editors, VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Volume 1066 of Communications in Computer and Information Science, pages 716-726, Springer, 2019. [doi]
Abstract is missing.