Abstract is missing.
- Flexible Composite Galois Field GF((2^m)^2) Multiplier DesignsM. Mohamed Asan Basiri, Sandeep K. Shukla. 3-14 [doi]
- Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input TransitionsManan Mewada, Mazad Zaveri, Anurag Lakhlani. 15-23 [doi]
- VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive FilterMohd Tasleem Khan, Shaik Rafi Ahamed. 24-35 [doi]
- Realization of Multiplier Using Delay Efficient Cyclic Redundant AdderK. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath. 36-47 [doi]
- Fast Architecture of Modular Inversion Using Itoh-Tsujii AlgorithmPravin Zode, Raghavendra B. Deshmukh, Abdus Samad. 48-55 [doi]
- Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES DevicesJatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra. 56-61 [doi]
- A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed ApplicationsNaman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury. 62-68 [doi]
- A Framework for Branch Predictor Selection with Aggregation on Multiple ParametersMoumita Das, Ansuman Banerjee, Bhaskar Sardar. 69-74 [doi]
- FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFTThilagavathy R, Susmitha Settivari, B. Venkataramani, M. Bhaskar. 75-80 [doi]
- Low Voltage, Low Power Transconductor for Low Frequency G_m -C FiltersHanumantha Rao G., Rekha S.. 83-92 [doi]
- An Improved Highly Efficient Low Input Voltage Charge Pump CircuitNaresh Kumar, Raja Hari Gudlavalleti, Subash Chandra Bose. 93-102 [doi]
- A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor StoragePallavi G. Darji, Chetan D. Parikh. 103-114 [doi]
- Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperature Induced VariationM. Santosh, Anjli Bansal, Jitendra Mishra, K. C. Behra, S. C. Bose. 115-126 [doi]
- FEM Based Device Simulator for High Voltage DevicesAshok Ray, Gaurav Kumar, Sushanta Bordoloi, Dheeraj Kumar Sinha, Pratima Agarwal, Gaurav Trivedi. 127-135 [doi]
- Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET TechnologySushma Srivastava, S. S. Rathod. 136-143 [doi]
- A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring OscillatorVivek Tyagi, M. S. Hashmi, Ganesh Raj, Vikas Rana. 144-152 [doi]
- Deterministic Shift Power Reduction in Test CompressionKanad Basu, Rishi Kumar, Santosh Kulkarni 0002, Rohit Kapur. 155-167 [doi]
- Pseudo-BIST: A Novel Technique for SAR-ADC TestingYatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan, Manish Sharma, Sabyasachi Das. 168-178 [doi]
- SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity AnalysisRahul Bhattacharya, S. H. M. Ragamai, Subindu Kumar. 179-190 [doi]
- A Cost Effective Technique for Diagnosis of Scan Chain FaultsSatyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag. 191-204 [doi]
- Multi-mode Toggle Random Access Scan to Minimize Test Application TimeAnshu Goel, Rohini Gulve. 205-216 [doi]
- Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip MultiprocessorsAvishek Choudhury, Biplab K. Sikdar. 217-224 [doi]
- Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETsAshish Soni, Abhijit Umap, Nihar R. Mohapatra. 227-238 [doi]
- Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher PerformanceSatish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas. 239-248 [doi]
- Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH SensorAjay Singh, Rakhi Narang, Manoj Saxena, Mridula Gupta. 249-258 [doi]
- Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCsAditya Japa, Harshita Vallabhaneni, Ramesh Vaddi. 259-269 [doi]
- An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA ImplementationJai Gopal Pandey, Tarun Goel, Abhijit Karmakar. 270-278 [doi]
- Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFETJ. Pathak, A. Darji. 279-286 [doi]
- Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam LithographyArindam Sinharay, Pranab Roy, Hafizur Rahaman. 287-295 [doi]
- Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File OrganizationSumanth Gudaparthi, Rahul Shrestha. 299-312 [doi]
- Performance-Enhanced d^2 -LBDR for 2D Mesh Network-on-ChipAnugrah Jain, Vijay Laxmi, Meenakshi Tripathi, Manoj Singh Gaur, Rimpy Bishnoi. 313-323 [doi]
- ACAM: Application Aware Adaptive Cache Management for Shared LLCSujit Kr Mahto, Newton. 324-336 [doi]
- Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCsN. S. Aswathy, R. S. Reshma Raj, Abhijit Das 0002, John Jose, V. R. Josna. 337-344 [doi]
- Defeating HaTCh: Building Malicious IP CoresAnshu Bhardwaj, Subir Kumar Roy. 345-353 [doi]
- Low Cost Circuit Level Implementation of PRESENT-80 S-BOXS. Shanthi Rekha, P. Saravanan. 354-362 [doi]
- Modeling and Analysis of Transient Heat for 3D ICSubhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman. 365-375 [doi]
- Memory Efficient Fractal-SPIHT Based Hybrid Image EncoderMamata Panigrahy, Nirmal Chandra Behera, B. Vandana, Indrajit Chakrabarti, Anindya Sundar Dhar. 376-387 [doi]
- Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A ReviewDivya Singh. 388-397 [doi]
- Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar CharacteristicsY. Sudha Vani, N. Usha Rani, Ramesh Vaddi. 398-405 [doi]
- Enhancing Retention Voltage for SRAMAnkit Rehani, Sujay Deb, Suprateek Shukla. 406-413 [doi]
- Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm TechnologiesAnand Ilakal, Anuj Grover. 414-420 [doi]
- Improving the Design of Nearest Neighbor Quantum Circuits in 2D SpaceNeha Chaudhuri, Chandan Bandyopadhyay, Hafizur Rahaman. 421-426 [doi]
- Delay and Frequency Investigations in Coupled MLGNR InterconnectsManish Joshi, Koduri Teja, Ashish Singh, Rohit Dhiman. 429-440 [doi]
- LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS CircuitsAmbika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma. 441-451 [doi]
- Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block LayerShubham Negi, Poornima Mittal, Brijesh Kumar. 452-462 [doi]
- Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate GeometryRakhi Narang, Mridula Gupta, Manoj Saxena. 463-473 [doi]
- A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \upmu m CMOSPurvi Patel, Biswajit Mishra, Dipankar Nagchoudhuri. 474-486 [doi]
- A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power ApplicationsSwaati, Bishnu Prasad Das. 487-495 [doi]
- Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design PerspectiveVandana Kumari, Manoj Saxena, Mridula Gupta. 496-503 [doi]
- A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA PlatformRourab Paul, Sandeep Kumar Shukla. 507-518 [doi]
- New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI ImplementationNaushad Ali, Bharat Garg. 519-532 [doi]
- FPGA-Based Smart Camera System for Real-Time Automated Video SurveillanceSanjay Singh, Sumeet Saurav, Ravi Saini, Atanendu S. Mandal, Santanu Chaudhury. 533-544 [doi]
- Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel EffectsB. Vandana, J. K. Das, S. K. Mohapatra, B. K. Kaushik. 545-556 [doi]
- Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video ProcessingPuja Ghosh, P. Rangababu. 557-569 [doi]
- A Custom Designed RISC-V ISA Compatible Processor for SoCKavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Amrutur Bharadwaj. 570-577 [doi]
- An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power ReductionJasmine Kaur Gulati, Bhanu Prakash, Sumit Darak. 581-593 [doi]
- Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA DesignsAyan Palchaudhuri, Anindya Sundar Dhar. 594-606 [doi]
- On Generation of Delay Test with Capture Power SafetyRohini Gulve, Nihar Hage. 607-618 [doi]
- A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoCProkash Ghosh, Jyotirmoy Ghosh. 619-627 [doi]
- A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCMVivek Tyagi, M. S. Hashmi, Ganesh Raj, Vikas Rana. 631-645 [doi]
- A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOSAntaryami Panigrahi, Abhipsa Parhi. 646-656 [doi]
- A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm ProcessMudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad. 657-666 [doi]
- Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS ProcessMunish Malik, Ajay Kumar, H. S. Jatana. 667-678 [doi]
- Fast FPGA Placement Using Analytical OptimizationSameer Pawanekar, Gaurav Trivedi. 681-693 [doi]
- A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic BiochipsArpan Chakraborty, Piyali Datta, Debasis Dhal, Rajat Kumar Pal. 694-706 [doi]
- Splitting and Transport of a Droplet with No External Actuation Force for Lab on Chip DevicesT. Pravinraj, Rajendra Patrikar. 707-717 [doi]
- Analytical Partitioning: Improvement over FMSameer Pawanekar, Gaurav Trivedi. 718-730 [doi]
- A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-ChipRajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar. 731-736 [doi]
- Droplet Position Estimator for Open EWOD System Using Open Source Computer VisionVandana Jain, Vasavi Devarasetty, Rajendra Patrikar. 737-741 [doi]
- Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC DecoderRituparna Choudhury, P. Rangababu. 742-750 [doi]
- A Formal Perspective on Effective Post-silicon Debug and Trace Signal SelectionBinod Kumar 0001, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita. 753-766 [doi]
- Translation Validation of Loop Invariant Code Optimizations Involving False ComputationsRamanuj Chouksey, Chandan Karfa, Purandar Bhaduri. 767-778 [doi]
- A Framework for Automated Feature Based Mixed-Signal Equivalence CheckingAntara Ain, Sayandeep Sanyal, Pallab Dasgupta. 779-791 [doi]
- xMAS Based Accurate Modeling and Progress Verification of NoCsSurajit Das, Chandan Karfa, Santosh Biswas. 792-804 [doi]
- Faulty TSVs Identification in 3D IC Using Pre-bond TestingDilip Kumar Maity, Surajit Kumar Roy, Chandan Giri. 805-812 [doi]