Sabyasachi Das - researchr alias

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Viewing Publication 1 - 13 from 13

2017

Pseudo-BIST: A Novel Technique for SAR-ADC TestingYatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan, Manish Sharma, Sabyasachi Das. vdat 2017: 168-178 [doi]

2008

Resource sharing among mutually exclusive sum-of-product blocks for area reductionSabyasachi Das, Sunil P. Khatri. todaes, 13(3), 2008. [doi]

A Timing-Driven Approach to Synthesize Fast Barrel ShiftersSabyasachi Das, Sunil P. Khatri. tcas, 55-II(1):31-35, 2008. [doi]

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area CharacteristicSabyasachi Das, Sunil P. Khatri. tvlsi, 16(3):326-331, 2008. [doi]

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum ExpressionsSabyasachi Das, Sunil P. Khatri. vlsid 2008: 635-640 [doi]

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-ProductsSabyasachi Das, Sunil P. Khatri. vlsid 2008: 653-659 [doi]

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and ShiftersSabyasachi Das, Sunil P. Khatri. vlsid 2008: 572-579 [doi]

2006

2004

2 radio and CPU/DSP/RAM/ROMGiuseppe Gramegna, Massimo Franciotta, Valentina Mandara, Nino G. Bellantone, Michele Vaiana, Mario Paporo, Marco Losi, Sabyasachi Das, Philip G. Mattos. cicc 2004: 81-84 [doi]

2002

An efficient and regular routing methodology for datapath designsusing net regularity extractionSabyasachi Das, Sunil P. Khatri. tcad, 21(1):93-101, 2002. [doi]

2001

A regularity-driven fast gridless detailed router for high frequency datapath designsSabyasachi Das, Sunil P. Khatri. ispd 2001: 130-135 [doi]

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