A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis

Farid N. Najm, Noel Menezes, Imad A. Ferzli. A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(3):574-591, 2007. [doi]

Abstract

Abstract is missing.