Michael Payer - researchr alias

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Viewing Publication 1 - 16 from 16

2003

A Platform for Construction and Integration of Digital IP BlocksMichael Payer. mbmv 2003: 131-131

2001

Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation)Michael Payer. it, 43(1):16-21, 2001. [doi]

2000

Industrial Experience with Formal VerificationMichael Payer. mbmv 2000: 9-16

1995

Model Checking in Industrial Hardware DesignJörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl. dac 1995: 298-303 [doi]

1993

The Siemens high-level synthesis system CALLASJ. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy. tvlsi, 1(3):244-253, 1993. [doi]

1992

Allocation algorithms based on path analysisReinaldo A. Bergamaschi, Raul Camposano, Michael Payer. integration, 13(3):283-299, 1992. [doi]

Data Part Optimizations in the CALLAS Synthesis EnvironmentJ. Biesenack, Norbert Wehn, A. Stoll, Michael Payer. ifip10-2 1993: 263-274

1991

1989

Finite State Machine Theory as a Tool for Construction of Systolic ArraysMichael Payer. eurocast 1990: 212-224

Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-TechnikMichael Payer. PhD thesis, University of Hamburg, Germany, 1989. [doi]

1988

Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-SchaltungenMichael Payer. gi 1988: 174-190

1987

Verification and validation of hierarchical CMOS gate array layoutsMichael Payer. jsa, 21(1-5):445-452, 1987. [doi]

1980

Systematischer Entwurf von MakroprozessorenMichael Payer. gi 1980: 541

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