Abstract is missing.
- Fast and Accurate Instruction Fetch and Branch PredictionBrad Calder, Dirk Grunwald. 2-11
- The Impact of Unresolved Branches on Branch Prediction Scheme PerformanceAdam R. Talcott, Wayne Yamamoto, Mauricio J. Serrano, Roger C. Wood, Mario Nemirovsky. 12-21
- Tradeoffs in Two-Level On-Chip CachingNorman P. Jouppi, Steven J. E. Wilton. 34-45
- Architectural Support for Performance Tuning: A Case Study on the SPARCcenter2000Ashok Singhal, Aaron J. Goldberg. 48-59
- Characterization of Alpha AXP Performance Using TP and SPEC WorkloadsZarka Cvetanovic, Dileep Bhandarkar. 60-70
- Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory MultiprocessorChitra Natarajan, Sanjay Sharma, Ravishankar K. Iyer. 71-80
- Evaluating the Memory Overhead Required for COMA ArchitecturesTruman Joe, John L. Hennessy. 82-93
- A Comparison of Message Passing and Shared Memory Architectures for Data Parallel ProgramsAlexander C. Klaiber, Henry M. Levy. 94-105
- Guarded Executing and Branch Prediction in Dynamic ILP ProcessorsDionisios N. Pnevmatikatos, Gurindar S. Sohi. 120-129
- Branch with Masked Squashing in Superpipelined ProcessorsChing-Long Su, Alvin M. Despain. 130-140
- Virtual Memory Mapped Network Interface for the SHRIMP MulticomputerMatthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg. 142-153
- Architecture and Evaluation of High-Speed Networking Subsystem for Distributed-Memory SystemsPeter Steenkiste, Michael Hemy, Todd W. Mummert, Brian Zill. 154-163
- Exploring the Design Space for a Shared-Cache MultiprocessorBasem A. Nayfeh, Kunle Olukotun. 166-175
- Impact of Sharing-Based Thread Placement on Multithreaded ArchitecturesRadhika Thekkath, Susan J. Eggers. 176-186
- Combined Performance Gains of Simple Cache Protocol ExtensionsFredrik Dahlgren, Michel Dubois, Per Stenström. 187-197
- Speculative Disambiguation: A Compilation Technique for Dynamic Memory DisambiguationAndrew S. Huang, Gert Slavenburg, John Paul Shen. 200-210
- Complexity/Performance Tradeoffs with Non-Blocking LoadsKeith I. Farkas, Norman P. Jouppi. 211-222
- A Performance Study of Software and Hardware Data Prefetching SchemesTien-Fu Chen, Jean-Loup Baer. 223-232
- RAID-II: A High-Bandwidth Network File ServerAnn L. Drapeau, Ken Shirriff, John H. Hartman, Ethan L. Miller, Srinivasan Seshan, Randy H. Katz, Ken Lutz, David A. Patterson, Edward K. Lee, Peter M. Chen, Garth A. Gibson. 234-244
- EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID ArchitecturesMario Blaum, Jim Brady, Jehoshua Bruck, Jai Menon. 245-254
- Crosshatch Disk Array for Improved Reliability and PerformanceSpencer W. Ng. 255-264
- METRO: A Router Architecture for High-Performance, Short-Haul Routing NetworksFrederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.. 266-277
- Ariadne - An Adaptive Router for Fault-Tolerant MulticomputersJames D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili. 278-288
- Compressionless Routing: A Framework for Adaptive and Fault-Tolerant RoutingJae H. Kim, Ziqiang Liu, Andrew A. Chien. 289-300
- The Stanford FLASH MultiprocessorJeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy. 302-313
- Software-Extended Coherent Shared Memory: Performance and CostDavid Chaiken, Anant Agarwal. 314-324
- Tempest and Typhoon: User-Level Shared MemorySteven K. Reinhardt, James R. Larus, David A. Wood. 325-336
- A Study of Single-Chip Processor/Cache Organizations for Large Numbers of TransistorsMatthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun. 338-347
- A Unified Architectural Tradeoff MethodologyChung-Ho Chen, Arun K. Somani. 348-357
- Optimal Allocation of On-Chip Memory for Multiple-API Operating SystemsDavid Nagle, Richard Uhlig, Trevor N. Mudge, Stuart Sechrest. 358-369
- Expected I-Cache Miss Rates via the Gap ModelRussell W. Quong. 372-383
- Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss RatioAndré Seznec. 384-393