Abstract is missing.
- An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300Michael A. Schuette, John Paul Shen. 2-11 [doi]
- A Quantitative Analysis of Locality in Dataflow ProgramsWilliam Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. 12-18 [doi]
- An Analysis of the Information Content of Address Reference StreamsJeffrey C. Becker, Arvin Park, Matthew K. Farrens. 19-24 [doi]
- Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue ProcessorsPohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu. 25-33 [doi]
- The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic SchedulingMichael Butler, Yale N. Patt. 34-41 [doi]
- Strategies for Branch Target BuffersBrian K. Bray, Michael J. Flynn. 42-50 [doi]
- Two-Level Adaptive Training Branch PredictionTse-Yu Yeh, Yale N. Patt. 51-61 [doi]
- Workload and Implementation Considerations for Dynamic Base Register CachingMatthew K. Farrens, Arvin Park. 62-68 [doi]
- Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data PrefetchingWilliam Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu. 69-73 [doi]
- Software Pipelining for Transport-Triggered ArchitecturesJan Hoogerbrugge, Henk Corporaal, Hans Mulder. 74-81 [doi]
- Software Pipelining: An Evaluation of Enhanced PipeliningReese B. Jones, Vicki H. Allan. 82-92 [doi]
- Efficient DAG Construction and Heuristic Calculation for Instruction SchedulingMark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt. 93-102 [doi]
- Code Duplication: An Assist for Global Instruction SchedulingDavid Bernstein, Doron Cohen, Hugo Krawczyk. 103-113 [doi]
- Implementation Optimization Techniques for Architecture Synthesis of Application-Specific ProcessorsMauricio Breternitz Jr., John Paul Shen. 114-123 [doi]
- ALPS: An Algorithm for Pipeline Data Path SynthesisRamesh Karri, Alex Orailoglu. 124-132 [doi]
- Increasing User Interaction During High-Level SynthesisRobert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland. 133-142 [doi]
- GRIP: Graphics Reduced Instruction ProcessorGautam B. Singh. 143-152 [doi]
- Viewing Instruction Set Design as an Optimization ProblemBruce K. Holmer, Alvin M. Despain. 153-162 [doi]
- DISC: Dynamic Instruction Stream ComputerMario Nemirovsky, Forrest Brewer, Roger C. Wood. 163-171 [doi]
- A New Technique for Induction Variable RemovalHaigeng Wang, Alexandru Nicolau, Roni Potasman. 172-180 [doi]
- Architecture and Programming of a VLIW Style Programmable Video Signal ProcessorGerben Essink, Emile H. L. Aarts, R. van Dongen, P. van Gerwen, Jan H. M. Korst, Kees A. Vissers. 181-188 [doi]
- On Reconfigurable On-Chip Data CachesFredrik Dahlgren, Per Stenström. 189-198 [doi]
- Executing Loops on a Fine-Grained MIMD ArchitectureSunah Lee, Rajiv Gupta. 199-205 [doi]
- Genetic Algorithms and Instruction SchedulingSteven J. Beaty. 206-211 [doi]
- GURPR:::*:::: A New Global Software Pipelining AlgorithmBogong Su, Jian Wang. 212-216 [doi]
- Register/File/Cache Microarchitecture Study Using VHDLSamarina Makhdoom, Daniel Tabak, Richard Auletta. 217-222 [doi]