William Y. Chen - researchr alias

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Viewing Publication 1 - 22 from 22

2000

The Intel IA-64 Compiler Code GeneratorJay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce. micro, 20(5):44-53, 2000. [doi]

1998

IMPACT: An Architectural Framework for Multiple-Instruction-Issue ProcessorsPohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu. isca 1998: 408-417 [doi]

1995

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined ProcessorsPohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu. TC, 44(3):353-370, 1995.

Three Architecutral Models for Compiler-Controlled Speculative ExecutionPohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu. TC, 44(4):481-494, 1995.

1994

Profile-assisted instruction schedulingWilliam Y. Chen, Scott A. Mahlke, Nancy J. Warter, Sadun Anik, Wen-mei W. Hwu. ijpp, 22(2):151-181, 1994. [doi]

Dynamic Memory Disambiguation Using the Memory Conflict BufferDavid M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu. asplos 1994: 183-193

1993

The Effect of Code Expanding Optimizations on Instruction Cache DesignWilliam Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu. TC, 42(9):1045-1057, 1993.

The superblock: An effective technique for VLIW and superscalar compilationWen-mei W. Hwu, Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Nancy J. Warter, Roger A. Bringmann, Roland G. Ouellette, Richard E. Hank, Tokuzo Kiyohara, Grant E. Haab, John G. Holm, Daniel M. Lavery. tjs, 7(1-2):229-248, 1993. [doi]

Register Connection: A New Approach to Adding Registers into Instruction Set ArchitecturesTokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu. isca 1993: 247-256

Sentinel Scheduling for VLIW and Superscalar ProcessorsScott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker. tocs, 11(4):376-408, 1993. [doi]

1992

Profile-guided Automatic Inline Expansion for C ProgramsPohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu. SPE, 22(5):349-369, 1992.

Tolerating First Level Memory Access Latency in High-Performance SystemsWilliam Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu. icpp 1992: 36-43

Using Profile Information to Assist Advaced Compiler Optimization and SchedulingWilliam Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Sadun Anik, Tokuzo Kiyohara, Nancy J. Warter, Daniel M. Lavery, Wen-mei W. Hwu, Richard E. Hank, John C. Gyllenhaal. lcpc 1993: 31-48

An efficient architecture for loop based data preloadingWilliam Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo. euromicro 1992: 92-101 [doi]

Tolerating data access latency with register preloadingWilliam Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang. ics 1992: 104-113 [doi]

Sentinel Scheduling for VLIW and Superscalar ProcessorsScott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker. asplos 1992: 238-247

Compiler Code Transformations for Superscalar-Based High Performance SystemsScott A. Mahlke, William Y. Chen, John C. Gyllenhaal, Wen-mei W. Hwu. sc 1992: 808-817

Effective compiler support for predicated execution using the hyperblockScott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann. euromicro 1992: 45-54 [doi]

1991

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