Table of Contents

• Retrospective: Banyan Networks for Partitioning Multiprocessor SystemsG. Jack Lipovski. 1 [doi]
• Retrospective: A Preliminary Architecture for a Basic Data Flow ProcessorJack B. Dennis. 2-4 [doi]
• Memory System Characterization of Commercial WorkloadsLuiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion. 3-14 [doi]
• Retrospective: Improving the Throughput of a Pipeline by Insertion of DelaysJanak H. Patel. 5 [doi]
• Retrospective: What Have We Learned from the PDP-11 - What We Have Learned from VAX and AlphaGordon Bell, William D. Strecker. 6-10 [doi]
• Retrospective: An Instruction Timing Model of CPU PerformanceLeonard J. Shustek, Bernard L. Peuto. 11-12 [doi]
• Retrospective: A Retrospective on High-Level Language Computer ArchitectureDavid R. Ditzel, David A. Patterson. 13-14 [doi]
• Retrospective: A Processor for a High-Performance Personal ComputerKenneth A. Pier. 17-19 [doi]
• Retrospective: A Study of Branch Prediction StrategiesJames E. Smith. 22-23 [doi]
• Retrospective: RISC I: A Reduced Instruction Set ComputerDavid A. Patterson, Carlo H. Séquin. 24-26 [doi]
• Retrospective: Decoupled Access/Execute ArchitecturesJames E. Smith. 27-28 [doi]
• Execution Characteristics of Desktop Applications on Windows NTDennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad. 27-38 [doi]
• Retrospective: Characterization of Processor Performance in the VAX-11/780Joel S. Emer, Douglas W. Clark. 37-38 [doi]
• An Analysis of Database Workload Performance on Simultaneous Multithreaded ProcessorsJack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh. 39-50 [doi]
• Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache MemoriesJanak H. Patel. 39-41 [doi]
• Retrospective: Implementing Precise Interrupts in Pipelined ProcessorsJames E. Smith. 42 [doi]
• Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal FunctionalityWen-mei W. Hwu, Yale N. Patt. 43-44 [doi]
• Retrospective: A Retrospective on the Warp MachinesThomas R. Gross, Monica S. Lam. 45-47 [doi]
• Retrospective: Memory Access Buffering in MultiprocessorsMichel Dubois, Christoph Scheurich. 48-50 [doi]
• Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined ProcessorsGurindar S. Sohi. 51-53 [doi]
• An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors WorkMarius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt. 52-61 [doi]
• Retrospective: the J-machineWilliam J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen. 54-58 [doi]
• Retrospective: On the Inclusion Properties for Multi-Level Cache HierarchiesJean-Loup Baer, Wen-Hann Wang. 59-60 [doi]
• Retrospective: Evaluation of Directory Dchemes for Cache CoherenceJohn L. Hennessy. 61-62 [doi]
• Branch Prediction Based on Universal Data Compression AlgorithmsEitan Federovsky, Meir Feder, Shlomo Weiss. 62-72 [doi]
• Retrospective: Weak Ordering - A New DefinitionSarita V. Adve, Mark D. Hill. 63-66 [doi]
• Retrospective: Memory Consistency and Event Ordering in Scalable Shared-Memory MultiprocessorsKourosh Gharachorloo. 67-70 [doi]
• Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch BuffersNorman P. Jouppi. 71-73 [doi]
• Modeling Program PredictabilityYiannakis Sazeides, James E. Smith. 73-84 [doi]
• Retrospective: Monsoon: An Explicit Token-Store ArchitectureDavid E. Culler, Gregory M. Papadopoulos. 74-76 [doi]
• Retrospective: IMPACT: An Architectural Framework for Multiple-Instruction IssueWen-mei W. Hwu. 77-79 [doi]
• Retrospective: The DASH Prototype: Implementation and PerformanceDaniel Lenoski, James Laudon. 80-82 [doi]
• Retrospective: Active Messages: A Mechanism for Integrating Computation and CommunicationThorsten von Eicken, David E. Culler, Klaus E. Schauser, Seth Copen Goldstein. 83-84 [doi]
• Retrospective: The Turn Model for Adaptive RoutingLionel M. Ni. 85-86 [doi]
• Multi-Level Texture Caching for 3D Graphics HardwareMichael Cox, Narendra Bhandri, Michael Shantz. 86-97 [doi]
• Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch PredictionTse-Yu Yeh, Yale N. Patt. 87-88 [doi]
• Retrospective: The Cedar SystemAlexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle Gallivan. 89-91 [doi]
• Retrospective: Virtual Memory Mapped Network Interface for the SHRIMP MulticomputerMatthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg. 92-94 [doi]
• Retrospective: The Stanford FLASH MultiprocessorJeffrey Kuskin. 95-97 [doi]
• Switcherland: A QoS Communication Architecture for Workstation ClustersHans Eberle, Erwin Oertli. 98-108 [doi]
• Retrospective: Tempest and Typhoon: User-Level Shared MemorySteven K. Reinhardt, James R. Larus, David A. Wood. 98-102 [doi]
• Retrospective: The MIT Alewife Machine: Architecture and PerformanceAnant Agarwal. 103-110 [doi]
• Declustered Disk Array Architectures with Optimal and Near-Optimal ParallelismGuillermo A. Alvarez, Walter A. Burkhard, Larry J. Stockmeyer, Flaviu Cristian. 109-120 [doi]
• Retrospective: Multiscalar ProcessorsGurindar S. Sohi. 111-114 [doi]
• Retrospective: Simultaneous Multithreading: Maximizing On-Chip ParallelismDean M. Tullsen, Susan J. Eggers, Henry M. Levy. 115-116 [doi]
• Banyan Networks for Partitioning Multiprocessor SystemsL. Rodney Goke, G. Jack Lipovski. 117-124 [doi]
• Confidence Estimation for Speculation ControlDirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun. 122-131 [doi]
• A Primlinary Architecture for a Basic Data-Flow ProcessorJack B. Dennis, David Misunas. 125-131 [doi]
• Pipeline Gating: Speculation Control for Energy ReductionSrilatha Manne, Artur Klauser, Dirk Grunwald. 132-141 [doi]
• Improving the Throughput of a Pipeline by Insertion of DelaysJanak H. Patel, Edward S. Davidson. 132-137 [doi]
• Computer Structures: What Have We Learned from the PDP-11?Gordon Bell, William D. Strecker. 138-151 [doi]
• Memory Dependence Prediction Using Store SetsGeorge Z. Chrysos, Joel S. Emer. 142-153 [doi]
• An Instruction Timing Model of CPU PerformanceBernard L. Peuto, Leonard J. Shustek. 152-165 [doi]
• Dynamic History-length Fitting: A Third Level of Adaptivity for Branch PredictionToni Juan, Sanji Sanjeevan, Juan J. Navarro. 155-166 [doi]
• Retrospective on High-Level Language Computer ArchitectureDavid R. Ditzel, David A. Patterson. 166-173 [doi]
• Accurate Indirect Branch PredictionKarel Driesen, Urs Hölzle. 167-178 [doi]
• Using Prediction to Accelerate Coherence ProtocolsShubhendu S. Mukherjee, Mark D. Hill. 179-190 [doi]
• A Processor for a High-Performance Personal ComputerButler W. Lampson, Kenneth A. Pier. 180-194 [doi]
• A Study of Branch Prediction StrategiesJames E. Smith. 202-215 [doi]
• Increasing TLB Reach Using Superpages Backed by Shadow MemoryMark R. Swanson, Leigh Stoller, John B. Carter. 204-213 [doi]
• Options for Dynamic Address Translation in COMAsXiaogang Qiu, Michel Dubois. 214-225 [doi]
• RISC I: A Reduced Instruction Set VLSI ComputerDavid A. Patterson, Carlo H. Séquin. 216-230 [doi]
• Integrated Predicated and Speculative Execution in the IMPACT EPIC ArchitectureDavid I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu. 227-237 [doi]
• Decoupled Access/Execute Computer ArchitecturesJames E. Smith. 231-238 [doi]
• Threaded Multiple Path ExecutionSteven Wallace, Brad Calder, Dean M. Tullsen. 238-249 [doi]
• The NYU Ultracomputer - Designing a MIMD, Shared-Memory Parallel MachineAllan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir. 239-254 [doi]
• Selective Eager Execution on the PolyPath ArchitectureArtur Klauser, Abhijit Paithankar, Dirk Grunwald. 250-259 [doi]
• Improving Trace Cache Effectiveness with Branch Promotion and Trace PackingSanjay J. Patel, Marius Evers, Yale N. Patt. 262-271 [doi]
• The Effect of Instruction Fetch Bandwidth on Value PredictionFreddy Gabbay, Avi Mendelson. 272-281 [doi]
• A Characterization of Processor Performance in the VAX-11/780Joel S. Emer, Douglas W. Clark. 274-283 [doi]
• Dynamic IPC/Clock Rate OptimizationDavid H. Albonesi. 282-292 [doi]
• A Low-Overhead Coherence Solution for Multiprocessors with Private Cache MemoriesMark S. Papamarcos, Janak H. Patel. 284-290 [doi]
• Implementation of Precise Interupts in Pipelined ProcessorsJames E. Smith, Andrew R. Pleszkun. 291-299 [doi]
• Performance Modeling and Code Partitioning for the DS ArchitectureYinong Zhang, George B. Adams III. 293-304 [doi]
• HPSm, a High Performance Restricted Data Flow Architecture Having Minimal FunctionalityWen-mei W. Hwu, Yale N. Patt. 300-308 [doi]
• Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU ProcessorStephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee. 306-317 [doi]
• Warp Architecture and ImplementationMarco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb. 309-319 [doi]
• Effects of Architectural and Technological Advances on the HP/Convex Exemplar s Memory and Communication PerformanceGheith A. Abandah, Edward S. Davidson. 318-329 [doi]
• Memory Access Buffering in MultiprocessorsMichel Dubois, Christoph Scheurich, Faye A. Briggs. 320-328 [doi]
• Instruction Issue Logic for High-Performance, Interruptable Pipelined ProcessorsGurindar S. Sohi, Sriram Vajapeyam. 329-336 [doi]
• Design Choices in the SHRIMP System: An Empirical StudyMatthias A. Blumrich, Richard Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li, Margaret Martonosi, Robert A. Shillner. 330-341 [doi]
• Architecture of a Message-Driven ProcessorWilliam J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills. 337-344 [doi]
• Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM MultiprocessorsVijayaraghavan Soundararajan, Mark Heinrich, Ben Verghese, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy. 342-355 [doi]
• On the Inclusion Properties for Multi-Level Cache HierarchiesJean-Loup Baer, Wen-Hann Wang. 345-352 [doi]
• An Evaluation of Directory Schemes for Cache CoherenceAnant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz. 353-362 [doi]
• Exploiting Spatial Locality in Data Caches Using Spatial FootprintsSanjeev Kumar, Christopher B. Wilkerson. 357-368 [doi]
• Weak Ordering - A New DefinitionSarita V. Adve, Mark D. Hill. 363-375 [doi]
• Low Load Latency Through Sum-Addressed Memory (SAM)William L. Lynch, Gary Lauterbach, Joseph I. Chamdani. 369-379 [doi]
• Memory Consistency and Event Ordering in Scalable Shared-Memory MultiprocessorsKourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip B. Gibbons, Anoop Gupta, John L. Hennessy. 376-387 [doi]
• Analytic Evaluation of Shared-memory Systems with ILP ProcessorsDaniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood. 380-391 [doi]
• Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch BuffersNorman P. Jouppi. 388-397 [doi]
• Monsoon: An Explicit Token-Store ArchitectureGregory M. Papadopoulos, David E. Culler. 398-407 [doi]
• IMPACT: An Architectural Framework for Multiple-Instruction-Issue ProcessorsPohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu. 408-417 [doi]
• The DASH Prototype: Implementation and PerformanceDaniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John L. Hennessy. 418-429 [doi]
• Active Messages: A Mechanism for Integrated Communication and ComputationThorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus E. Schauser. 430-440 [doi]
• The Turn Model for Adaptive RoutingChristopher J. Glass, Lionel M. Ni. 441-450 [doi]
• Alternative Implementations of Two-Level Adaptive Branch PredictionTse-Yu Yeh, Yale N. Patt. 451-461 [doi]
• The Cedar System and an Initial Performance StudyDavid J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu. 462-472 [doi]
• Virtual Memory Mapped Network Interface for the SHRIMP MulticomputerMatthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg. 473-484 [doi]
• The Stanford FLASH MultiprocessorJeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy. 485-496 [doi]
• Tempest and Typhoon: User-Level Shared MemorySteven K. Reinhardt, James R. Larus, David A. Wood. 497-508 [doi]
• The MIT Alewife Machine: Architecture and PerformanceAnant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz. 509-520 [doi]
• Multiscalar ProcessorsGurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar. 521-532 [doi]
• Simultaneous Multithreading: Maximizing On-Chip ParallelismDean M. Tullsen, Susan J. Eggers, Henry M. Levy. 533-544 [doi]