Abstract is missing.
- Architectural Requirements of Parallel Scientific Applications with Explicit CommunicationRobert Cypher, Alex Ho, Smaragda Konstantinidou, Paul Messina. 2-13
- Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale MultiprocessorsEdward Rothberg, Jaswinder Pal Singh, Anoop Gupta. 14-25
- Design Tradeoffs for Software-Managed TLBsDavid Nagle, Richard Uhlig, Timothy J. Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown. 27-38
- Architectural Support for Translation Table Management in Large Address Space MachinesJerome C. Huck, Jim Hays. 39-50
- The TickerTAIP Parallel RAID ArchitecturePei Cao, Swee Boon Lim, Shivakumar Venkataraman, John Wilkes. 52-63
- Parity Logging Overcoming the Small Write Problem in Redundant Disk ArraysDaniel Stodolsky, Garth A. Gibson, Mark Holland. 64-75
- The Architecture of a Fault-Tolerant Cached RAID ControllerJai Menon, Jim Cortney. 76-86
- The Detection and Elimination of Useless Misses in MultiprocessorsMichel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström. 88-97
- Adaptive Cache Coherency for Detecting Migratory Shared DataAlan L. Cox, Robert J. Fowler. 98-108
- An Adaptive Cache Coherence Protocol Optimized for Migratory SharingPer Stenström, Mats Brorsson, Lars Sandberg. 109-118
- Register Relocation: Flexible Contexts for MultithreadingCarl A. Waldspurger, William E. Weihl. 120-130
- Multiple Threads in Cyclic Register WindowsYasuo Hidaka, Hanpei Koike, Hidehiko Tanaka. 131-142
- Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network TechnologySandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel. 144-155
- Mechanisms for Cooperative Shared MemoryDavid A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt. 156-167
- A Case for Two-Way Skewed-Associative CachesAndré Seznec. 169-178
- Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped CachesAnant Agarwal, Steven D. Pudar. 179-190
- Cache Write Policies and PerformanceNorman P. Jouppi. 191-201
- Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240Eric L. Boyd, Edward S. Davidson. 203-212
- The Cedar System and an Initial Performance StudyDavid J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner. 213-223
- The J-Machine Multicomputer: An Architectural EvaluationMichael D. Noakes, Deborah A. Wallach, William J. Dally. 224-235
- 16-Bit vs. 32-Bit Instructions for Pipelined MicroprocessorsJohn Bunda, Donald S. Fussell, Roy M. Jenevein, William C. Athas. 237-246
- Register Connection: A New Approach to Adding Registers into Instruction Set ArchitecturesTokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu. 247-256
- A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch HistoryTse-Yu Yeh, Yale N. Patt. 257-266
- Limitations of Cache Prefetching on a Bus-Based MultiprocessorDean M. Tullsen, Susan J. Eggers. 278-288
- Transactional Memory: Architectural Support for Lock-Free Data StructuresMaurice Herlihy, J. Eliot B. Moss. 289-300
- Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally. 302-313
- Improving AP1000 Parallel Computer Performance with Message CommunicationTakeshi Horie, Kenichi Hayashi, Toshiyuki Shimizu, Hiroaki Ishihata. 314-325
- Performance of Cached DRAM Organizations in Vector SupercomputersWei-Chung Hsu, James E. Smith. 327-336
- The Chinese Remainder Theorem and the Prime Memory SystemQ. S. Gao. 337-340
- Odd Memory Systems May be Quite InterestingAndré Seznec, Jacques Lenfant. 341-350
- A Comparison of Adaptive Wormhole Routing AlgorithmsRajendra V. Boppana, Suresh Chalasani. 351-360