Abstract is missing.
- The SNAP-1 Parallel AI PrototypeRonald F. DeMara, Dan I. Moldovan. 2-11 [doi]
- GT-EP: A Novel High-Performance Real-Time ArchitectureWei Siong Tan, H. Russ, Cecil O. Alford. 13-21 [doi]
- IXM2: A Parallel Associative ProcessorTetsuya Higuchi, Tatsumi Furuya, Ken ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu. 22-31 [doi]
- An Architecture for Software-Controlled Data PrefetchingAlexander C. Klaiber, Henry M. Levy. 43-53 [doi]
- Data Prefetching in Multiprocessor Vector Cache MemoriesJohn W. C. Fu, Janak H. Patel. 54-63 [doi]
- Reducing Memory Contention in Shared Memory MultiprocessorsDavid T. Harper III. 66-73 [doi]
- Pseudo-Randomly Interleaved MemoryB. Ramakrishna Rau. 74-83 [doi]
- Evaluation of Memory System ExtensionsKai Li, Karin Petersen. 84-93 [doi]
- High Performance Interprocessor Communication through Optical Wavelength Division Multiple Access ChannelsPatrick W. Dowd. 96-105 [doi]
- Race-Free Interconnection Networks and Multiprocessor ConsistencyAnders Landin, Erik Hagersten, Seif Haridi. 106-115 [doi]
- Deadlock-Free Multicast Wormhole Routing in Multicomputer NetworksXiaola Lin, Lionel M. Ni. 116-125 [doi]
- Implementing a Cache for a High-Performance GaAs MicroprocessorKunle Olukotun, Trevor N. Mudge, Richard B. Brown. 138-147 [doi]
- Classification and Performance Evaluation of Instruction Buffering TechniquesLizy Kurian John, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai. 150-159 [doi]
- OHMEGA: A VLSI Superscalar Processor Architecture for Numerical ApplicationsMasaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota. 160-168 [doi]
- An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club BenchmarksSriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu. 170-179 [doi]
- Instruction Level Profiling and Evaluation of the IBM/6000Chriss Stephens, Bryce Cogswell, John Heinlein, Gregory Palmer, John Paul Shen. 180-189 [doi]
- Performance Prediction and Tuning on a MultiprocessorRobert T. Dimpsey, Ravishankar K. Iyer. 190-199 [doi]
- Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event TracesC. W. Oehlrich, Andreas Quick. 202-211 [doi]
- Chaos Router: Architecture and PerformanceSmaragda Konstantinidou, Lawrence Snyder. 212-221 [doi]
- Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time ApplicationsShridhar B. Shukla, Dharma P. Agrawal. 222-231 [doi]
- Detecting Data Races on Weak Memory SystemsSarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer. 234-243 [doi]
- On the Validity of Trace-Driven Simulation for MultiprocessorsEric J. Koldinger, Susan J. Eggers, Henry M. Levy. 244-253 [doi]
- Comparative Evaluation of Latency Reducing and Tolerating TechniquesAnoop Gupta, John L. Hennessy, Kourosh Gharachorloo, Todd C. Mowry, Wolf-Dietrich Weber. 254-263 [doi]
- IMPACT: An Architectural Framework for Multiple-Instruction-Issue ProcessorsPohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu. 266-275 [doi]
- Single Instruction Stream Parallelism is Greater Than TwoMichael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow. 276-286 [doi]
- Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software TechniquesStephen W. Melvin, Yale N. Patt. 287-296 [doi]
- Comparison of Hardware and Software Cache Coherence SchemesSarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon. 298-308 [doi]
- Modeling the Performance of Limited Pointers Directories for Cache CoherenceRichard Simoni, Mark Horowitz. 309-319 [doi]
- Flexible Register Management for Sequential ProgramsDonna J. Quammen, D. Richard Miller. 320-329 [doi]
- The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation StrategyDavid G. Bradlee, Susan J. Eggers, Robert R. Henry. 330-339 [doi]
- Multithreading: A Revisionist View of Dataflow ArchitecturesGregory M. Papadopoulos, Kenneth R. Traub. 342-351 [doi]
- Multi-Threaded VectorizationTzi-cker Chiueh. 352-361 [doi]
- Strategies for Achieving Improved Processor ThroughputMatthew K. Farrens, Andrew R. Pleszkun. 362-369 [doi]
- Adaptive Storage Management for Very Large Virtual/Real Storage SystemsToyohiko Kagimasa, Kikuo Takahashi, Toshiaki Mori, Seiichi Yoshizumi. 372-379 [doi]
- Modeling and Measurement of the Impact of Input/Output on System PerformanceJanaki Akella, Daniel P. Siewiorek. 390-399 [doi]