Abstract is missing.
- Separating Data and Control Transfer in Distributed Operating SystemsChandramohan A. Thekkath, Henry M. Levy, Edward D. Lazowska. 2-11
- Scheduling and Page Migration for Multiprocessor Compute ServersRohit Chandra, Scott Devine, Ben Verghese, Anoop Gupta, Mendel Rosenblum. 12-24
- Reactive Synchronization Algorithms for MultiprocessorsBeng-Hong Lim, Anant Agarwal. 25-35
- Integration of Message Passing and Shared Memory in the Stanford FLASH MultiprocessorJohn Heinlein, Kourosh Gharachorloo, Scott Dresser, Anoop Gupta. 38-50
- Software Overhead in Messaging Layers: Where Does the Time Go?Vijay Karamcheti, Andrew A. Chien. 51-60
- Where is Time Spent in Message-Passing and Shared-Memory Programs?Satish Chandra, James R. Larus, Anne Rogers. 61-73
- Performance of a Hardware-Assisted Real-Time Garbage CollectorWilliam J. Schmidt, Kelvin D. Nilsen. 76-85
- eNVy: A Non-Volatile, Main Memory Storage SystemMichael Wu, Willy Zwaenepoel. 86-97
- Resource Allocation in a High Clock Rate MicroprocessorMichael Upton, Thomas Huff, Trevor N. Mudge, Richard B. Brown. 98-109
- Hardware and Software Support for Efficient Exception HandlingChandramohan A. Thekkath, Henry M. Levy. 110-119
- A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User ApplicationsPramod V. Argade, David K. Charles, Craig Taylor. 122-131
- Trap-driven Simulation with Tapeworm IIRichard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest. 132-144
- Contrasting Characteristics and Cache Performance of Technical and Multi-User Commercial WorkloadsAnn Marie Grizzaffi Maynard, Colette M. Donnelly, Bret R. Olszewski. 145-156
- Avoiding Conflict Misses Dynamically in Large Direct-Mapped CachesBrian N. Bershad, Dennis Lee, Theodore H. Romer, J. Bradley Chen. 158-170
- Surpassing the TLB Performance of Superpages with Less Operating System SupportMadhusudhan Talluri, Mark D. Hill. 171-182
- Dynamic Memory Disambiguation Using the Memory Conflict BufferDavid M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu. 183-193
- AP1000+: Architectural Support of PUT/GET Interface for Parallelizing CompilerKenichi Hayashi, Tsunehisa Doi, Takeshi Horie, Yoichi Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu, Hiroaki Ishihata, Tatsuya Shindo. 196-207
- LCM: Memory System Support for Parallel Language ImplementationJames R. Larus, Brad Richards, Guhan Viswanathan. 208-218
- The Performance Advantages of Integrating Block Data Trabsfer in Cache-Coherent MultiprocessorsSteven Cameron Woo, Jaswinder Pal Singh, John L. Hennessy. 219-229
- Improving the Accuracy of Static Branch Prediction Using Branch CorrelationCliff Young, Michael D. Smith. 232-241
- Reducing Branch Costs via Branch AlignmentBrad Calder, Dirk Grunwald. 242-251
- Compiler Optimizations for Improving Data LocalitySteve Carr, Kathryn S. McKinley, Chau-Wen Tseng. 252-262
- DCG: An Efficient, Retargetable Dynamic Code Generation SystemDawson R. Engler, Todd A. Proebsting. 263-272
- The Performance Impact of Flexibility in the Stanford FLASH MultiprocessorMark Heinrich, Jeffrey Kuskin, David Ofelt, John Heinlein, Joel Baxter, Jaswinder Pal Singh, Richard Simoni, Kourosh Gharachorloo, David Nakahira, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy. 274-285
- Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence ProtocolsJonas Skeppstedt, Per Stenström. 286-296
- Fine-grain Access Control for Distributed Shared MemoryIoannis Schoinas, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, James R. Larus, David A. Wood. 297-306
- Interleaving: A Multithreading Technique Targeting Multiprocessors and WorkstationsJames Laudon, Anoop Gupta, Mark Horowitz. 308-318
- Hardware Support for Fast Capability-based AddressingNicholas P. Carter, Stephen W. Keckler, William J. Dally. 319-327
- The Effectiveness of Multiple Hardware ContextsRadhika Thekkath, Susan J. Eggers. 328-337