Table of Contents

• An investigation of the performance of various dynamic scheduling techniquesMichael Butler, Yale N. Patt. 1-9 [doi]
• On the limits of program parallelism and its smoothabilityKevin B. Theobald, Guang R. Gao, Laurie J. Hendren. 10-19 [doi]
• On the instruction-level characteristics of scalar code in highly-vectorized scientific applicationsSriram Vajapeyam, Wei-Chung Hsu. 20-28 [doi]
• Exploiting instruction-level parallelism with the conjugate register file schemeMeng-chou Chang, Feipei Lai, Rung-Ji Shang. 29-32 [doi]
• Limitation of superscalar microprocessor performanceThang Tran, Chuan-lin Wu. 33-36 [doi]
• Branch merging for effective exploitation of instruction-level parallelismChien-Ming Chen, Yunn Yen Chen, Chung-Ta King. 37-40 [doi]
• A non-deterministic scheduler for a software pipelining compilerAlessandro De Gloria, Paolo Faraboschi, Mauro Olivieri. 41-44 [doi]
• Effective compiler support for predicated execution using the hyperblockScott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann. 45-54 [doi]
• An efficient resource-constrained global scheduling technique for superscalar and VLIW processorsSoo-Mook Moon, Kemal Ebcioglu. 55-71 [doi]
• Enhanced region scheduling on a program dependence graphV. H. Allen, J. Janardhan, R. M. Lee, M. Srinivas. 72-80 [doi]
• Executing compressed programs on an embedded RISC architectureAndrew Wolfe, Alex Chanin. 81-91 [doi]
• An efficient architecture for loop based data preloadingWilliam Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo. 92-101 [doi]
• Stride directed prefetching in scalar processorsJohn W. C. Fu, Janak H. Patel, Bob L. Janssens. 102-110 [doi]
• Controlling and sequencing a heavily pipelined floating-point operatorAndré Seznec, Karl Courtel. 111-114 [doi]
• Data path issues in a highly concurrent machineAugustus K. Uht, Darin B. Johnson. 115-118 [doi]
• A VLIW architecture for optimal execution of branch-intensive loopsBogong Su, Wei Zhao, Zhizhong Tang, Stanley Habib. 119-124 [doi]
• Y-Pipe: a conditional branching scheme without pipeline delaysMichael J. Knieser, Christos A. Papachristou. 125-128 [doi]
• A comprehensive instruction fetch mechanism for a processor supporting speculative executionTse-Yu Yeh, Yale N. Patt. 129-139 [doi]
• Microarchitecture support for dynamic scheduling of acyclic task graphsCarl J. Beckmann, Constantine D. Polychronopoulos. 140-148 [doi]
• Interlock collapsing ALU for increased instruction-level parallelismNadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis. 149-157 [doi]
• Code generation schema for modulo scheduled loopsB. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai. 158-169 [doi]
• Enhanced modulo scheduling for loops with conditional branchesNancy J. Warter, Grant E. Haab, Krishna Subramanian, John W. Bockhaus. 170-179 [doi]
• A dynamic-programming technique for compacting loopsSteven R. Vegdahl. 180-188 [doi]
• Exploiting instruction-level parallelism: the multithreaded approachPhilip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar. 189-192 [doi]
• MISC: a Multiple Instruction Stream ComputerGary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun. 193-196 [doi]
• Code scheduling for VLIW/superscalar processors with limited register filesTokuzo Kiyohara, John C. Gyllenhaal. 197-201 [doi]
• Tradeoffs in processor/memory interfaces for superscalar processorsThomas M. Conte. 202-205 [doi]
• Translation hint buffers to reduce access time of physically-addressed instruction cachesBrian K. Bray, Michael J. Flynn. 206-209 [doi]
• Modifying VM hardware to reduce address pin requirementsMatthew K. Farrens, Arvin Park, Gary S. Tyson. 210-213 [doi]
• Toward zero-cost branches using instruction registersKent D. Wilken, David W. Goodwin. 214-217 [doi]
• Ordering functions for improving memory reference locality in a shared memory multiprocessor systemYoufeng Wu. 218-221 [doi]
• The effect of page allocation on cachesWilliam L. Lynch, Brian K. Bray, Michael J. Flynn. 222-225 [doi]
• Performance evaluation of instruction scheduling on the IBM RISC System/6000David Bernstein, Doron Cohen, Yuval Lavon, Vladimir Rainish. 226-235 [doi]
• Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processorsManoj Franklin, Gurindar S. Sohi. 236-245 [doi]
• Performance analysis and design methodology for a scalable superscalar architectureTakaaki Kato, Toshihisa Ono, Nader Bagherzadeh. 246-255 [doi]
• Lookahead schedulingSteven J. Beaty. 256-259 [doi]
• Dominator-path scheduling: a global scheduling methodPhilip H. Sweany, Steven J. Beaty. 260-263 [doi]
• A shape matching approach for scheduling fine-grained parallelismBrian A. Malloy, Rajiv Gupta, Mary Lou Soffa. 264-267 [doi]
• A new approach to schedule operations across nested-ifs and nested-loopsShih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang. 268-271 [doi]
• An out-of-order superscalar processor with speculative execution and fast, precise interruptsHarry Dwyer, Hwa C. Torng. 272-281 [doi]
• StaCS: a Static Control Superscalar architectureBenoît Dupont de Dinechin. 282-291 [doi]
• Partitioned register files for VLIWs: a preliminary analysis of tradeoffsAndrea Capitanio, Nikil D. Dutt, Alexandru Nicolau. 292-300 [doi]