Philip H. Sweany - researchr alias

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Viewing Publication 1 - 29 from 29

2014

Debugging teacher certification (abstract only)Jian Zhang, Philip H. Sweany. sigcse 2014: 730 [doi]

2008

FPGA implementations of elliptic curve cryptography and Tate pairing over a binary fieldHao Li, Jian Huang, Philip H. Sweany, Dijiang Huang. jsa, 54(12):1077-1088, 2008. [doi]

2007

An FPGA implementation of elliptic curve cryptography for future secure web transactionJian Huang, Hao Li, Philip H. Sweany. ISCApdcs 2007: 296-301

Feasibility of decoupling memory management from the execution pipelineWentong Li, Mehran Rezaei, Krishna M. Kavi, Afrin Naz, Philip H. Sweany. jsa, 53(12):927-936, 2007. [doi]

2006

Speculative Thread Execution in a Multithreaded Dataflow ArchitectureWentong Li, Krishna M. Kavi, Afrin Naz, Philip H. Sweany. ISCApdcs 2006: 102-107

A Study of Reconfigurable Split Data Caches and Instruction CachesAfrin Naz, Krishna M. Kavi, Philip H. Sweany, Wentong Li. ISCApdcs 2006: 235-240

Tiny split data-caches make big performance impact for embedded applicationsAfrin Naz, Krishna M. Kavi, Wentong Li, Philip H. Sweany. jec, 2(2):207-219, 2006. [doi]

2005

Improving data cache performance with integrated use of split caches, victim cache and stream buffersAfrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany. sigarch, 33(3):41-48, 2005. [doi]

2004

Automatic data partitioning for the agere payload plus network processorSteve Carr, Philip H. Sweany. cases 2004: 238-247 [doi]

A Study of Separate Array and Scalar CachesAfrin Naz, Krishna M. Kavi, Philip H. Sweany, Mehran Rezaei. hpcs 2004: 157-164

Improving data cache performance with integrated use of split caches, victim cache and stream buffersAfrin Naz, Mehran Rezaei, Krishna Kavi, Philip H. Sweany. medea 2004: 41-48 [doi]

2003

An experimental evaluation of scalar replacement on scientific benchmarksSteve Carr, Philip H. Sweany. SPE, 33(15):1419-1445, 2003. [doi]

2002

Loop fusion for clustered VLIW architecturesYi Qian, Steve Carr, Philip H. Sweany. lctrts 2002: 112-119 [doi]

Optimizing Loop Performance for Clustered VLIW ArchitecturesYi Qian, Steve Carr, Philip H. Sweany. IEEEpact 2002: 271-280 [doi]

2001

Loop Transformations for Architectures with Partitioned Register BanksXianglong Huang, Steve Carr, Philip H. Sweany. lctrts 2001: 48-55

Loop Transformations for Architectures with Partitioned Register BanksXianglong Huang, Steve Carr, Philip H. Sweany. PLDI 2001: 48-55 [doi]

2000

Global Register PartitioningJason Hiser, Steve Carr, Philip H. Sweany. IEEEpact 2000: 13-23 [doi]

Register Assignment for Software Pipelining with Partitioned Register BanksJason Hiser, Steve Carr, Philip H. Sweany, Steven J. Beaty. ipps 2000: 211-218 [doi]

1999

Improving software pipelining with hardware support for self-spatial loadsSteve Carr, Philip H. Sweany. sigarch, 27(1):55-58, 1999. [doi]

1998

Building a Retargetable Local Instruction SchedulerVicki H. Allan, Steven J. Beaty, Bogong Su, Philip H. Sweany. SPE, 28(3):249-283, 1998.

Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without CopiesPhilip H. Sweany, Steve Carr, Brett L. Huber. dtj, 10(1), 1998. [doi]

1997

Modulo Scheduling with Cache Reuse InformationChen Ding, Steve Carr, Philip H. Sweany. europar 1997: 1079-1083

1996

Improving Software Pipelining with Unroll-and-JamSteve Carr, Chen Ding, Philip H. Sweany. hicss 1996: 183-192 [doi]

Extending List Scheduling to Consider Execution FrequencyMichael J. Bourke III, Philip H. Sweany, Steven J. Beaty. hicss 1996: 193-202 [doi]

1995

CRAIG: a practical framework for combining instruction scheduling and register assignmentThomas S. Brasier, Philip H. Sweany, Steven J. Beaty, Steve Carr. IEEEpact 1995: 11-18 [doi]

1992

Dominator-path scheduling: a global scheduling methodPhilip H. Sweany, Steven J. Beaty. euromicro 1992: 260-263 [doi]

1990

Post-compaction register assignment in a retargetable compilerPhilip H. Sweany, Steven J. Beaty. euromicro 1990: 107-116 [doi]

1988

Horizon: A Retargetable Compiler for Horizontal MicroarchitecturesRobert A. Mueller, Michael R. Duda, Philip H. Sweany, Jack S. Walicki. TSE, 14(5):575-583, 1988. [doi]

1987

Trace scheduling optimization in a retargetable microcode compilerMichael A. Howland, Robert A. Mueller, Philip H. Sweany. euromicro 1987: 106-114 [doi]

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