Abstract is missing.
- Instruction sets and their implementationsMichael J. Flynn. 1-6 [doi]
- VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessorsMarco Danelutto, Marco Vanneschi. 7-16 [doi]
- A software pipelining based VLIW architecture and optimizing compilerBogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu. 17-27 [doi]
- A fine-grained MIMD architecture based upon register channelsRajiv Gupta. 28-37 [doi]
- Hardware implementation of a general multi-way jump mechanismSoo-Mook Moon, Scott D. Carson, Ashok K. Agrawala. 38-45 [doi]
- Software pipelining: a comparison and improvementReese B. Jones, Vicki H. Allan. 46-56 [doi]
- Using a lookahead window in a compaction-based parallelizing compilerToshio Nakatani, Kemal Ebcioglu. 57-68 [doi]
- Realistic scheduling: compaction for pipelined architecturesAlexandru Nicolau, Roni Potasman. 69-79 [doi]
- An evaluation system for application specific architecturesAlessandro De Gloria, Paolo Faraboschi. 80-89 [doi]
- A framework for high-speed controller designJ. M. Mulder, R. J. Portier, A. Srivastava. 90-96 [doi]
- High-level microprogramming: an optimizing C compiler for a processing element of a CAD acceleratorPaul Kenyon, Prathima Agrawal, Sharad C. Seth. 97-106 [doi]
- Post-compaction register assignment in a retargetable compilerPhilip H. Sweany, Steven J. Beaty. 107-116 [doi]
- Motivation and framework for using genetic algorithms for microcode compactionSteven J. Beaty, Darrell Whitley, Gearold Johnson. 117-124 [doi]
- Ideograph/Ideogram: framework/hardware for eager evaluationS. ShouHan Wang, Augustus K. Uht. 125-134 [doi]
- An instruction reoderer for pipelined computersJong-Jiann Shieh, Christos A. Papachristou. 135-142 [doi]
- Optimization on instruction reorganizationFeipei Lai, Hung-Chang Lee, Chun-Luh Lee. 143-148 [doi]
- Automatic synthesis of a dual-PLA controller with a counterDavid Binger, David Knapp. 149-157 [doi]
- Interconnection synthesis with geometric constraintsForrest Brewer, Barry M. Pangrle, Andrew Seawright. 158-165 [doi]
- An application of L systems to local microcode synthesisFarhad Mavaddat, M. Mahmood, Mantis H. M. Cheng. 166-175 [doi]
- The selection of optimal cache lines for microprocessor-based controllersTsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin. 183-192 [doi]
- Address compression through base register cachingArvin Park, Matthew K. Farrens. 193-199 [doi]
- A memory management unit and cache controller for the MARS systemFeipei Lai, Chyuan-Yow Wu, Tai-Ming Parng. 200-208 [doi]
- An evaluation of functional unit lengths for single-chip processorsMatthew K. Farrens, Andrew R. Pleszkun. 209-215 [doi]
- A multiple floating point coprocessor architectureLawrence Rauchwerger, P. Michael Farmwald. 216-222 [doi]
- A barrel shift microsystem for parallel processingReuven Bakalash, Zhong Xu. 223-229 [doi]
- PRISM architecture: parallel and pipeline featuresBeverly Gocal. 230-236 [doi]
- Topologies for the parallel backtracking Prolog engineL. Campanale, M. De Blasi, A. Gentile, F. Greco. 237-242 [doi]
- A high-level microprogrammed processorChristian Iseli, Eduardo Sanchez. 244-251 [doi]
- SMDSS - a structured microcode development and simulation systemDjahida Smati, Jerry Hwang, Christos A. Papachristou. 252-259 [doi]
- On the testing of microprogrammed processorS. Hwang, Rochit Rajsuman, Yashwant K. Malaiya. 260-266 [doi]
- A weighted technique for programmable logic devices minimizationC. Hwa Chang, Hammad K. Azzam. 267-274 [doi]
- Microprogramming heritage of RISC designLiwen Shih. 275-280 [doi]
- A survey on bit dimension optimization strategies of microprogramsSunil R. Das, Amiya Nayak. 281-291 [doi]
- A model of a microprogrammed functional-oriented computing unitMonica Alderighi, Giacomo R. Sechi. 292-298 [doi]