Abstract is missing.
- Guests editor's introduction1-2 [doi]
- Energy aware memory architecture configurationHanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin. 3-9 [doi]
- DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latencyHyo-Joong Suh, Sung Woo Chung. 10-16 [doi]
- Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratiosSami Yehia, Jean-Francois Collard, Olivier Temam. 17-24 [doi]
- Locality analysis to control dynamically way-adaptable cachesHiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa. 25-32 [doi]
- SH-X: an embedded processor core for consumer appliancesFumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori. 33-40 [doi]
- Improving data cache performance with integrated use of split caches, victim cache and stream buffersAfrin Naz, Mehran Rezaei, Krishna Kavi, Philip H. Sweany. 41-48 [doi]
- Speculative execution for hiding memory latencyAlex Pajuelo, Antonio González 0001, Mateo Valero. 49-56 [doi]
- The impact of traffic aggregation on the memory performance of networking applicationsJavier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero. 57-62 [doi]