Abstract is missing.
- Parallelism in Mainstream Enterprise Platforms of the FutureDileep Bhandarkar. 3 [doi]
- An Evaluation of Data-Parallel Compiler Support for Line-Sweep ApplicationsDaniel G. Chavarría-Miranda, John M. Mellor-Crummey. 7-17 [doi]
- Increasing and Detecting Memory Address CongruenceSamuel Larsen, Emmett Witchel, Saman P. Amarasinghe. 18-29 [doi]
- Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread PerformanceGautham K. Dorai, Donald Yeung. 30 [doi]
- Compiler-Controlled Caching in Superword Register Files for Multimedia Extension ArchitecturesJaewook Shin, Jacqueline Chame, Mary W. Hall. 45-55 [doi]
- Effective Compilation Support for Variable Instruction Set ArchitectureJack Liu, Timothy Kong, Fred C. Chow. 56-67 [doi]
- A Framework for Parallelizing Load/Stores on Embedded ProcessorsXiaotong Zhuang, Santosh Pande, John S. Greenland Jr.. 68 [doi]
- Workload Design: Selecting Representative Program-Input PairsLieven Eeckhout, Hans Vandierendonck, Koenraad De Bosschere. 83-94 [doi]
- Dataflow Frequency Analysis Based on Whole Program PathsBernhard Scholz, Eduard Mehofer. 95-103 [doi]
- Quantifying Instruction CriticalityEric Tune, Dean M. Tullsen, Brad Calder. 104 [doi]
- The Role of Computational Science in Energy Efficiency and Renewable EnergySteve Hammond. 117 [doi]
- Application Transformations for Energy and Performance-Aware Device ManagementTaliver Heath, Eduardo Pinheiro, Jerry Hom, Ulrich Kremer, Ricardo Bianchini. 121-130 [doi]
- Leakage Energy Management in Cache HierarchiesLin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam. 131-140 [doi]
- Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic PowerSteve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott. 141 [doi]
- The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA MultiprocessorsManuel E. Acacio, José González, José M. García, José Duato. 155-164 [doi]
- Predicting Conditional Branches With Fusion-Based Hybrid PredictorsGabriel H. Loh, Dana S. Henry. 165 [doi]
- Speculative Sequential Consistency with Little Custom StorageChris Gniady, Babak Falsafi. 179-188 [doi]
- Cost-Effective Compiler Directed Memory Prefetching and BypassingDaniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero. 189-198 [doi]
- Using the Compiler to Improve Cache Replacement DecisionsZhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, Charles C. Weems. 199 [doi]
- Software Bubbles: Using Predication to Compensate for Aliasing in Software PipelinesBenjamin Goldberg, Emily Crutcher, Chad Huneycutt, Krishna V. Palem. 211-221 [doi]
- Speculative Alias Analysis for Executable CodeManel Fernández, Roger Espasa. 222-231 [doi]
- Cost Effective Memory Dependence Prediction using Speculation Levels and Color SetsSoner Önder. 232 [doi]
- The Computational Grid: Aggregating Performance and Enhanced Capability from Federated ResourcesRichard Wolski. 245 [doi]
- Just-In-Time Java? Compilation for the Itanium® ProcessorTatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Tabatabai. 249-258 [doi]
- Eliminating Exception Constraints of Java Programs for IA-64Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani. 259 [doi]
- Optimizing Loop Performance for Clustered VLIW ArchitecturesYi Qian, Steve Carr, Philip H. Sweany. 271-280 [doi]
- Exploiting Pseudo-Schedules to Guide Data Dependence Graph PartitioningAlex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli. 281-290 [doi]
- Efficient Interconnects for Clustered MicroarchitecturesJoan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato. 291 [doi]
- SIGARCH Conference GuidelinesDavid A. Patterson. 301 [doi]