Abstract is missing.
- Register allocation sensitive region schedulingCindy Norris, Lori L. Pollock. 1-10 [doi]
- CRAIG: a practical framework for combining instruction scheduling and register assignmentThomas S. Brasier, Philip H. Sweany, Steven J. Beaty, Steve Carr. 11-18 [doi]
- Compiler techniques for data prefetching on the PowerPCDavid Bernstein, Doron Cohen, Ari Freund. 19-26 [doi]
- Multithreading with the EM-4 distributed-memory multiprocessorAndrew Sohn, Chinhyun Kim, Mitsuhisa Sato. 27-36 [doi]
- Ordered multithreading: a novel technique for exploiting thread-level parallelismMasato Motomura, Toshiaki Inoue, Sunao Torii, Akihiko Konagaya. 37-48 [doi]
- Increasing superscalar performance through multistreamingWayne Yamamoto, Mario Nemirovsky. 49-58 [doi]
- A design study of the EARTH multiprocessorHerbert H. J. Hum, Olivier Maquelin, Kevin B. Theobald, Xinmin Tian, Xinan Tang, Guang R. Gao, Phil Cupryk, Nasser Elmasri, Laurie J. Hendren, Alberto Jimenez, Shoba Krishnan, Andres Marquez, Shamir Merali, Shashank S. Nemawarkar, Prakash Panangaden, Xun Xue, Yingchun Zhu. 59-68 [doi]
- A compiler algorithm that reduces read latency in ownership-based cache coherence protocolsJonas Skeppstedt, Per Stenström. 69-78 [doi]
- Direct-mapped versus set-associative pipelined cachesNathalie Drach, André Seznec, Daniel Windheiser. 79-88 [doi]
- The influence of branch prediction table interference on branch prediction scheme performanceAdam R. Talcott, Mario Nemirovsky, Roger C. Wood. 89-98 [doi]
- Using predicated execution to improve the performance of a dynamically scheduled machine with speculative executionPo-Yung Chang, Eric Hao, Yale N. Patt, Pohua P. Chang. 99-108 [doi]
- Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreadingPradeep K. Dubey, Kevin O'Brien, Kathryn M. O'Brien, Charles Barton. 109-121 [doi]
- Analysis of communications and overhead reduction in multithreaded executionLucas Roh, Walid A. Najjar. 122-130 [doi]
- Control of loop parallelism in multithreaded codeBhanu Shankar, Lucas Roh, A. P. Wim Böhm, Walid A. Najjar. 131-139 [doi]
- Effects of data bundling in non-strict data structuresEunha Rho, Sang-Yong Han, Heunghwan Kim, Daejoon Hwang. 140-148 [doi]
- Practical approach to single assignment codePatricia Prather Pineo, Mary Lou Soffa. 149-158 [doi]
- A simple algorithm for the generation of efficient loop structuresMichel Cosnard, Michel Loi. 159-167 [doi]
- Data flow analysis of parallel programsJürgen Vollmer. 168-177 [doi]
- Scheduling optimization through iterative refinementMayez Al-Mouhamed, Adel Al-Maasarani. 178-184 [doi]
- Mappings for communication minimization using distribution and alignmentCatherine Mongenet. 185-193 [doi]
- An analytical model of high performance superscalar-based multiprocessorsDavid H. Albonesi, Israel Koren. 194-203 [doi]
- Evaluating the impact of advanced memory systems on compiler-parallelized codesEvan Torrie, Chau-Wen Tseng, Margaret Martonosi, Mary W. Hall. 204-213 [doi]
- An empirical evaluation of the Convex SPP-1000 hierarchical shared memory systemThomas L. Sterling, Daniel Savarese, Phillip Merkey, Kevin Olson. 214-223 [doi]
- A partitioning-independent paradigm for nested data parallelismDean Engelhardt, Andrew L. Wendelborn. 224-233 [doi]
- IPF for real-time image processing on massively parallel architecturesY. Robin. 234-243 [doi]
- Handling block-cyclic distributed arrays in Vienna Fortran 90Siegfried Benkner. 244-253 [doi]
- Translation of serial recursive codes to parallel SIMD codesAbdou Youssef. 254-263 [doi]
- The meeting graph: a new model for loop cyclic register allocationChristine Eisenbeis, Sylvain Lelait, Bruno Marmol. 264-267 [doi]
- Transformation of functional specifications of finite difference methods to parallel distributed codesKanad Roy, Carl McCrosky. 268-272 [doi]
- Using compilers for heterogeneous system designRainer Leupers, Peter Marwedel. 273-276 [doi]
- Decomposed software pipelining with reduced register requirementJian Wang, Andreas Krall, M. Anton Ertl. 277-280 [doi]
- Self-parallelization of sequential object codesRudolph N. Rechtschaffen, Kattamuri Ekanadham. 281-283 [doi]
- A loop parallelization technique for linear dependence vectorTeruaki Kitasuka, Kazuki Joe, Dale Schouten, Akira Fukuda, Keijiro Araki. 285-289 [doi]
- Allocating registers in multiple instruction-issuing processorsChristine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn. 290-293 [doi]
- Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical codeSoo-Mook Moon. 294-297 [doi]
- A proposal of self-cleanup cacheShin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita. 298-301 [doi]
- Performance impact of architectural features during binary to binary translationBryce Cogswell, Zary Segall. 302-305 [doi]
- Automatic generation of loop scheduling for VLIWCristina Barrado, Jesús Labarta, Eduard Ayguadé, Mateo Valero. 306-309 [doi]
- From functional equations to Occam programs: systolizing compilationElena Trichina. 310-314 [doi]