Table of Contents

• BEAM: bus encoding based on instruction-set-aware memoriesYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. 3-8 [doi]
• Irredundant address bus encoding techniques based on adaptive codebooks for low powerSatoshi Komatsu, Masahiro Fujita. 9-14 [doi]
• Multi-parametric improvements for embedded systems using code-placement and address bus codingSri Parameswaran, Jörg Henkel, Haris Lekatsas. 15-21 [doi]
• Memory access pattern analysis and stream cache design for multimedia applicationsJungHee Lee, Chanik Park, Soonhoi Ha. 22-27 [doi]
• A statistical gate delay model for intra-chip and inter-chip variabilitiesKen-ichi Okada, Kento Yamaoka, Hidetoshi Onodera. 31-36 [doi]
• A fast and accurate method for interconnect current calculationMuzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan. 37-42 [doi]
• Calculating the effective capacitance for the RC interconnect in VDSM technologiesSoroush Abbaspour, Massoud Pedram. 43-48 [doi]
• Reduction of crosstalk noise by optimizing 3-D configuration of the routing gridAtsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura. 49-52 [doi]
• Design tools for 3-D integrated circuitsShamik Das, Anantha Chandrakasan, Rafael Reif. 53-56 [doi]
• An on-line approach for power minimization in QoS sensitive systemsJennifer L. Wong, Gang Qu, Miodrag Potkonjak. 59-64 [doi]
• Energy minimization of real-time tasks on variable voltage processors with transition energy overheadYumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen. 65-70 [doi]
• Register aware scheduling for distributed cache clustered architectureZhong Wang, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha. 71-76 [doi]
• Data partitioning for maximal scratchpad usageManish Verma, Stefan Steinke, Peter Marwedel. 77-83 [doi]
• SAT-based sequential depth computationMaher N. Mneimneh, Karem A. Sakallah. 87-92 [doi]
• Logic verification based on diagnosis techniquesAndreas G. Veneris, Alexander Smith, Magdy S. Abadir. 93-98 [doi]
• Algorithms for compacting error tracesYirng-An Chen, Fang-Sung Chen. 99-103 [doi]
• Transaction-based waveform analysis for IP selectionJian Liu, Eugene Shragowitz. 104-107 [doi]
• An automatic interconnection rectification technique for SoC design integrationChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. 108-111 [doi]
• Typing abstractions and management in a component frameworkFrederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta. 115-122 [doi]
• Event-driven observability enhanced coverage analysis of C programs for functional validationFarzan Fallah, Indradeep Ghosh, Masahiro Fujita. 123-128 [doi]
• Trace-driven rapid pipeline architecture evaluation scheme for ASIP designJun Kyoung Kim, Tag Gon Kim. 129-134 [doi]
• A hardware/software partitioning algorithm for SIMD processor coresKoichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki. 135-140 [doi]
• Approximate formulae approach for efficient inductance extractionAtsushi Kurokawa, Takashi Sato, Hiroo Masuda. 143-148 [doi]
• Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSFTakashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto. 149-155 [doi]
• A metric for analyzing effective on-chip inductive couplingGuoan Zhong, Cheng-Kok Koh, Kaushik Roy. 156-161 [doi]
• Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnectsJun Chen, Lei He. 162-167 [doi]
• Recent developments in ESD protection for RF ICsAlbert Wang. 171-178 [doi]
• Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit designKazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama. 179-183 [doi]
• Behavioral modeling of EM devices by selective orthogonal matrix least-squares methodYuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai. 184-188 [doi]
• A BDD-based fast heuristic algorithm for disjoint decompositionTomas Bengtsson, Andrés Martinelli, Elena Dubrova. 191-196 [doi]
• Logic optimization for asynchronous speed independent controllers using transduction methodHiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya. 197-202 [doi]
• Technology mapping for low leakage power and high speed with hot-carrier effect considerationChang Woo Kang, Massoud Pedram. 203-208 [doi]
• Synthesis of high performance low power PTL circuitsDebasis Samanta, M. C. Dharmadeep, Ajit Pal. 209-212 [doi]
• A technology mapping algorithm for heterogeneous FPGAsChi-Chou Kao, Yen-Tai Lai. 213-216 [doi]
• Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTLMohamed-Anouar Dziri, Firaz Samet, Flávio Rech Wagner, Wander O. Cesário, Ahmed Amine Jerraya. 219-224 [doi]
• Towards on-chip fault-tolerant communicationTudor Dumitras, Sam Kerner, Radu Marculescu. 225-232 [doi]
• Energy-aware mapping for tile-based NoC architectures under performance constraintsJingcao Hu, Radu Marculescu. 233-239 [doi]
• Adaptive wire adjustment for bounded skew Clock Distribution NetworkHaydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili. 243-248 [doi]
• Power minimization by clock root gatingQi Wang, Sumit Roy 0003. 249-254 [doi]
• BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extractionTaotao Lu, Zeyi Wang, Xianlong Hong. 255-260 [doi]
• Improving boundary element methods for parasitic extractionShu Yan, Jianguo Liu 0001, Weiping Shi. 261-267 [doi]
• Statistical delay computation considering spatial correlationsAseem Agarwal, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda. 271-276 [doi]
• Predicting short circuit power from timing modelsEmrah Acar, Ravishankar Arunachalam, Sani R. Nassif. 277-282 [doi]
• RCLK-VJ network reduction with Hurwitz polynomial approximationZhanhai Qin, Chung-Kuan Cheng. 283-291 [doi]
• Gate-level simulation of quantum circuitsGeorge F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes. 295-301 [doi]
• Enhanced symbolic simulation for efficient verification of embedded array systemsTao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir. 302-307 [doi]
• Hardware verification using ANSI-C programs as a referenceEdmund M. Clarke, Daniel Kroening. 308-311 [doi]
• Evaluation of multiple-output logic functions using decision diagramsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 312-315 [doi]
• A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraintsSatoshi Tayu. 319-324 [doi]
• Multi-level placement for large-scale mixed-size IC designsChin-Chih Chang, Jason Cong, Xin Yuan. 325-330 [doi]
• Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pairChikaaki Kodama, Kunihiro Fujiyoshi. 331-337 [doi]
• An extended representation of Q-sequence for optimizing channel-adjacency and routing-costChangwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani. 338-341 [doi]
• Non-slicing floorplans with boundary constraints using generalized polish expressionDe-Sheng Chen, Chang-Tzu Lin, Yiwen Wang 0003. 342-345 [doi]
• Anatomy of platform-based design: is it the savior of UDSM SoC design crisis?Tadahiko Nakamura, Takahide Inoue, Bob Altizer, Ken Chen, Jun Iwamura, Masasuke Kishi, Grant Martin, Augusto De Oliveira. 349 [doi]
• Efficient LUT-based FPGA technology mapping for power minimizationHao Li, Wai-Kei Mak, Srinivas Katkoori. 353-358 [doi]
• Optimal reconfiguration sequence managementSoheil Ghiasi, Majid Sarrafzadeh. 359-365 [doi]
• On improving FPGA routability applying multi-level switch boxesJiping Liu, Hongbing Fan, Yu-Liang Wu. 366-369 [doi]
• An image retrieval system using FPGAsKoji Nakano, Etsuko Takamichi. 370-373 [doi]
• Logic foundry: rapid prototyping of FPGA-based DSP systemsGary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima. 374-381 [doi]
• Advanced power management techniques: going beyond intelligent shutdownLuca Benini. 385-389 [doi]
• Design methodology of low-power microprocessorsToshihiro Hattori. 390-393 [doi]
• Design methodology of low-power CMOS RF-ICsTsuneo Tsukahara, Mitsuru Harada, Mamoru Ugajin, Junichi Kodate, Akihiro Yamagishi. 394-399 [doi]
• Minimizing total power by simultaneous Vdd/Vth assignmentAshish Srivastava, Dennis Sylvester. 400-403 [doi]
• A low power CMOS circuit with Variable Souce Scheme (VSCMOS)Takeo Yasuda, Kohji Hosokawa. 404-407 [doi]
• Fast buffer planning and congestion optimization in interconnect-driven floorplanningKeith W. C. Wong, Evangeline F. Y. Young. 411-416 [doi]
• Interconnect-driven floorplanning by searching alternative packingsChiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou. 417-422 [doi]
• Noise-aware buffer planning for interconnect-driven floorplanningKatherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang. 423-426 [doi]
• Floorplanning with power supply noise avoidanceHung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong. 427-430 [doi]
• Simultaneous floorplanning and buffer block planningIris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao. 431-434 [doi]
• A buffer planning algorithm based on dead space redistributionSong Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu. 435-438 [doi]
• VCore-based design methodologyMichiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida. 441-445 [doi]
• Synthesis for SoC architecture using VCoresHiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada. 446-452 [doi]
• VCore-based platform for SoC designYoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki. 453-458 [doi]
• VCDS tool demonstrationRafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka. 459 [doi]
• Adaptive computing: what can it do, where can it go?Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott. 463 [doi]
• DARPA's adaptive computing systems programJose L. Muñoz. 464 [doi]
• Applications of adaptive computing systems for signal processing challengesBrian Schott, Peter Bellows, Matthew French, Robert Parker. 465-470 [doi]
• Interactive ray tracing on reconfigurable SIMD MorphoSysHaitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel Lois Anido, Milagros Fernández. 471-476 [doi]
• An overview of a compiler for mapping MATLAB programs onto FPGAsPrith Banerjee. 477-482 [doi]
• Issues in debugging highly parallel FPGA-based applications derived from source codeK. Scott Hemmert, Brad L. Hutchings. 483-488 [doi]
• Implementation of the super-systolic array for convolutionJae-Jin Lee, Gi-Yong Song. 491-494 [doi]
• Design of a scalable RSA and ECC crypto-processorMing-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu. 495-498 [doi]
• A reconfigurable, power-scalable rake receiver IP for W-CDMAA. Bianco, Alberto Dassatti, Maurizio Martina, Andrea Molino, Fabrizio Vacca. 499-502 [doi]
• Robust high-performance low-power carry select adderWoopyo Jeong, Kaushik Roy. 503-506 [doi]
• Full-custom vs. standard-cell design flow: an adder case studyHenrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson. 507-510 [doi]
• A 500-MHz low-power five-port CMOS register fileJiajing Wang, Qianling Zhang. 511-514 [doi]
• An effective SDRAM power mode management scheme for performance and energy sensitive embedded systemsNing-Yaun Ker, Chung-Ho Chen. 515-518 [doi]
• Branch predictor design and performance estimation for a high performance embedded microprocessorSang-Hyuk Lee, Il-kwan Kim, Lynn Choi. 519-522 [doi]
• Accelerating design space exploration using pareto-front arithmeticsChristian Haubelt, Jürgen Teich. 525-531 [doi]
• Quality-driven design by bitwidth optimization for video applicationsYun Cao, Hiroto Yasuura. 532-537 [doi]
• Arbitrary long digit integer sorter HW/SW co-designShun-Wen Cheng. 538-543 [doi]
• Roles of funding agencies in technology-driven economic developmentKazuo Nakajima, Brian Schott, Tokinori Kozawa, Jose L. Muñoz, Wolfgang Rosenstiel, Sakae Takahashi, Chen-Wen Wu. 547 [doi]
• Legal protection for semiconductor Intellectual Property (IP)Yoichi Oshima. 551-555 [doi]
• Design and implementation of a video-oriented network-interface-card systemMing-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang. 559-560 [doi]
• A highly efficient AES cipher chipChih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu. 561-562 [doi]
• Implementation of fast CRC calculationTomas Henriksson, Dake Liu. 563-564 [doi]
• Design of a CMOS test chip for package models and I/O characteristics verificationChetan Despande, Tom Chen. 565-566 [doi]
• A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architectureMasanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama, Kenji Mochizuki, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi. 567-568 [doi]
• Speech encoding and encryption in VLSIK. Kalyan Chakravarthy, M. B. Srinivas. 569-570 [doi]
• The design of an i8080A instruction compatible processor with extended memory addressChiaki Kon, Naohiko Shimizu. 571-572 [doi]
• The design of a USB device controller IYOYOYOTomoaki Kouyama, Hibiki Nano, Chiaki Kon, Naohiko Shimizu. 573-574 [doi]
• MAPLE chip: a processing element for a static scheduling centric multiprocessorKenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano. 575-576 [doi]
• Finding the best system design flow for a high-speed JPEG encoderKazuo Sakiyama, Patrick Schaumont, Ingrid Verbauwhede. 577-578 [doi]
• The design of PCI bus interfaceHaruyasu Hayasaka, Hiroaki Haramiishi, Naohiko Shimizu. 579-580 [doi]
• Low-power digital CDMA receiverJa-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou. 581-582 [doi]
• Hardware implementation of an EAN-13 bar code decoderJeroen De Maeyer, Harald Devos, Wim Meeus, Peter Verplaetse, Dirk Stroobandt. 583-584 [doi]
• Error correction circuit using difference-set cyclic codeYukihiro Kato, Tomokazu Morita. 585-586 [doi]
• Design of a digital CDMA receiverI. Vijay Kumar, M. B. Srinivas. 587-588 [doi]
• Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologiesMasanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera. 589-590 [doi]
• A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitryTetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda. 591-592 [doi]
• Run-time energy estimation in system-on-a-chip designsJosef Haid, Gerald Kaefer, Christian Steger, Reinhold Weiss. 595-599 [doi]
• SEA: fast power estimation for micro-architecturesPraveen Kalla, Jörg Henkel, Xiaobo Sharon Hu. 600-605 [doi]
• HyPE: hybrid power estimation for IP-based programmable systemsXun Liu, Marios C. Papaefthymiou. 606-609 [doi]
• An efficient IP-level power model for complex digital circuitsChih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou. 610-613 [doi]
• A hierarchical analysis methodology for chip-level power delivery with realizable model reductionYu-Min Lee, Charlie Chung-Ping Chen. 614-618 [doi]
• Optimality and scalability study of existing placement algorithmsChin-Chih Chang, Jason Cong, Min Xie 0004. 621-627 [doi]
• IBM's 50 Million gate ASICsJürgen Koehl, David E. Lackey, George W. Doerre. 628-634 [doi]
• Silicon virtual prototyping: the new cockpit for nanometer chip designWei-Jin Dai, Dennis Huang, Chin-Chih Chang, Michel Courtoy. 635-639 [doi]
• Design flow and methodology for 50M gate ASICAlok Mehrotra, Lukas P. P. P. van Ginneken, Yatin Trivedi. 640-647 [doi]
• Efficient loop-back testing of on-chip ADCs and DACsHak-soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh. 651-656 [doi]
• A novel LCD driver testing technique using logic test channelsChauchin Su, Wei-Juo Wang, Chih-hu Wang, I. S. Tseng. 657-662 [doi]
• An implementation of memory-based on-chip analogue test signal generationSalvador Mir, Luís Rolíndez, Christian Domigues, Libor Rufer. 663-668 [doi]
• Delta-sigma modulator based mixed-signal BIST architecture for SoCChee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang. 669-674 [doi]
• Capturing and analyzing requirement: in case of software and applying to hardwareAkira Kawaguchi. 677-682 [doi]
• A comparison of the RTU hardware RTOS with a hardware/software RTOSJaehwan Lee, Vincent John Mooney III, Anders Daleby, Karl Ingström, Tommy Klevin, Lennart Lindh. 683-688 [doi]
• Linux kernel customization for embedded systems by using call graph approachChe-Tai Lee, Zeng-Wei Hong, Jim-Min Lin. 689-692 [doi]
• Topology selection for energy minimization in embedded networksDexin Li, Pai H. Chou, Nader Bagherzadeh. 693-696 [doi]
• Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial applicationJulia Dushina, Mike Benjamin, Daniel Geist. 699-704 [doi]
• Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designsAnurag Tiwari, Karen A. Tomko. 705-711 [doi]
• A novel approach for digital waveform compressionEdwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn. 712-715 [doi]
• A deep submicron power estimation methodology adaptable to variations between power characterization and estimationDaniel Eckerbert, Per Larsson-Edefors. 716-719 [doi]
• Congestion driven incremental placement algorithm for standard cell layoutZhuoyuan Li, Weimin Wu, Xianlong Hong. 723-728 [doi]
• Performance-driven multi-level clustering for combinational circuitsChin-Ngai Sze, Ting-Chi Wang. 729-740 [doi]
• Cross talk driven placementJinan Lou, Wei Chen. 735-740 [doi]
• VLSI module placement with pre-placed modules and considering congestion using solution space smoothingSheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu. 741-744 [doi]
• A path-based timing-driven quadratic placement algorithmWenting Hou, Xianlong Hong, Weimin Wu, Yici Cai. 745-748 [doi]
• Experience in critical path selection for deep sub-micron delay test and timing validationJing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng. 751-756 [doi]
• On effective criterion of path selection for delay testingMasayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura. 757-762 [doi]
• DFT timing design methodology for at-speed BISTYasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto. 763-768 [doi]
• An automated method for test model generation from switch level circuitsTim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir. 769-774 [doi]
• Using red-black interval trees in device-level analog placement with symmetry constraintsFlorin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy. 777-782 [doi]
• Current-driven wire planning for electromigration avoidance in analog circuitsJens Lienig, Göran Jerke. 783-788 [doi]
• Efficient DDD-based term generation algorithm for analog circuit behavioral modelingSheldon X.-D. Tan, C.-J. Richard Shi. 789-794 [doi]
• 5Gbps serial link transmitter with pre-emphasisChih-Hsien Lin, Chung-Hong Wang, Shyh-Jye Jou. 795-800 [doi]
• Low power synthesis of finite state machines with mixed D and T flip-flopsAli Iranli, Peyman Rezvani, Massoud Pedram. 803-808 [doi]
• Don't cares in logic minimization of extended finite state machinesYunjian Jiang, Robert K. Brayton. 809-815 [doi]
• Performance optimization of synchronous control units for datapaths with variable delay arithmetic unitsEuiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya. 816-819 [doi]
• Integer linear programming-based synthesis of skewed logic circuitsAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy. 820-823 [doi]
• Highly scalable algorithms for rectilinear and octilinear Steiner treesAndrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky. 827-833 [doi]
• UTACO: a unified timing and congestion optimizing algorithm for standard cell global routingTong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu. 834-839 [doi]
• The Y-architecture: yet another on-chip interconnect solutionHongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng. 840-847 [doi]
• A novel timing-driven global routing algorithm considering coupling effects for high performance circuit designJingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu. 847-850 [doi]
• Graph matching-based algorithms for array-based FPGA segmentation design and routingJai-Ming Lin, Song-Ra Pan, Yao-Wen Chang. 851-854 [doi]
• Routing-aware scan chain orderingPuneet Gupta, Andrew B. Kahng, Stefanus Mantik. 857-862 [doi]
• Multiple test set generation method for LFSR-based BISTYouhua Shi, Zhe Zhang. 863-868 [doi]
• A seed selection procedure for LFSR-based random pattern generatorsKenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki. 869-874 [doi]
• Efficient BIST design for sequential machines using FiF-FoF values in machine statesSamir Roy, Ujjwal Maulik, Sanghamitra Bandyopadhyay, S. Basu, Biplab Kumar Sikdar. 875-878 [doi]
• A new design-for-test technique for reducing SOC test timeC. V. Guru Rao, D. Roy Chowdhury. 879-882 [doi]
• Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulationXinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren. 885-890 [doi]
• A frequency separation macromodel for system-level simulation of RF circuitsXin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi. 891-896 [doi]
• Nonlinear distortion analysis via linear-centric modelsPeng Li, Lawrence T. Pileggi. 897-903 [doi]
• Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifierJinho Park, Kiyong Choi, David J. Allstot. 904-907 [doi]