Chi-Chou Kao - researchr alias

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Viewing Publication 1 - 25 from 25

2023

Optimizing FPGA-Based Convolutional Neural Network PerformanceChi-Chou Kao. jcsc, 32(15), October 2023. [doi]

Performance-oriented FPGA-based convolution neural network designsChi-Chou Kao. mta, 82(14):21019-21030, 2023. [doi]

2020

Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable ArchitecturesChi-Chou Kao. jcsc, 29(2), 2020. [doi]

Performance-driven parallel reconfigurable computing architecture for multi-standard video decodingChi-Chou Kao. mta, 79(41-42):30583-30599, 2020. [doi]

2019

Design and Implementation of Stereoscopic Image GenerationChi-Chou Kao. jcsc, 28(8):1950133, 2019. [doi]

2017

Designs of Low Power Snoop for Multiprocessor System on ChipChi-Chou Kao, Yi-Ciang Lin. vlsisp, 88(1):83-89, 2017. [doi]

Stereoscopic image generation with depth image based renderingChi-Chou Kao. mta, 76(11):12981-12999, 2017. [doi]

2015

Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable ArchitecturesChi-Chou Kao. tpds, 26(3):858-867, 2015. [doi]

Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers RestrictionChi-Chou Kao. vlsisp, 79(1):99-104, 2015. [doi]

2013

Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost DesignsChi-Chou Kao, Yen-Tai Lai. jcsc, 22(5), 2013. [doi]

E-Health Design of EEG Signal Classification for Epilepsy DiagnosisChi-Chou Kao. isbast 2013: 67-71 [doi]

2012

Laplacian-based H.264 intra-prediction mode decisionChi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng. chinacom 2012: 638-641 [doi]

2011

BDD-based synthesis for mixed CMOS/PTL logicChi-Chou Kao. ijcta, 39(9):923-932, 2011. [doi]

Heuristic Algorithms for Constructing Interference-Free and Delay-Constrained Multicast Trees for Wireless Mesh NetworksWen-Lin Yang, Chi-Chou Kao, Cheng-Huang Tung. itiis, 5(2):269-286, 2011. [doi]

2010

An efficient reflection invariance region-based image retrieval frameworkChi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin. imst, 20(2):155-161, 2010. [doi]

A Performance-Driven Rotational Invariant Image Retrieval SystemYen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh. jise, 26(6):2009-2022, 2010. [doi]

2009

A Novel Digital Pixel Sensor SystemYen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao. iscas 2009: 2297-2300 [doi]

2008

Computer-aided crosstalk minimisation design for system-on-chipChi-Chou Kao. iet-cdt, 2(1):23-29, 2008. [doi]

2007

A High Flexibility Design for Clock Distribution Network in System on ChipChi-Chou Kao. jcsc, 16(1):51-63, 2007. [doi]

2005

An efficient algorithm for finding the minimal-area FPGA technology mappingChi-Chou Kao, Yen-Tai Lai. todaes, 10(1):168-186, 2005. [doi]

2004

Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restrictionChi-Chou Kao, Yen-Tai Lai. aspdac 2004: 719-724 [doi]

2003

Design of echo cancellation and noise elimination for speech enhancementChi-Chou Kao. tce, 49(4):1468-1473, 2003. [doi]

A technology mapping algorithm for heterogeneous FPGAsChi-Chou Kao, Yen-Tai Lai. aspdac 2003: 213-216 [doi]

1999

A routability and performance driven technology mapping algorithm for LUT based FPGA designsChi-Chou Kao, Yen-Tai Lai. iscas 1999: 474-477 [doi]

A quadratic programming method for interconnection crosstalk minimizationYen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh. iscas 1999: 270-273 [doi]

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