Prith Banerjee - researchr alias

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Viewing Publication 1 - 20 from 20

2022

Hybrid Digital Twins: A Primer on Combining Physics-Based and Data Analytics ApproachesMatt Adams, Xiao Li, Lucas Boucinha, Sameer S. Kher, Prith Banerjee, Jose Luis Gonzalez. IEEE Software, 39(2):47-52, 2022. [doi]

2011

Everything as a Service: Powering the New Information EconomyPrith Banerjee, Rich Friedrich, Cullen Bash, P. Goldsack, Bernardo A. Huberman, J. Manley, Chandrakant D. Patel, Parthasarathy Ranganathan, A. Veitch. Computer, 44(3):36-43, 2011. [doi]

Resource optimization and deadlock prevention while generating streaming architectures from ordinary programsLei Gao, Gaurav Mittal, David Zaretsky, Prith Banerjee. ahs 2011: 9-16 [doi]

2010

An Intelligent IT Infrastructure for the FuturePrith Banerjee. icdcn 2010: 1 [doi]

Open Innovation at HP LabsPrith Banerjee, Rich Friedrich, L. Morell. Computer, 43(11):88-90, 2010. [doi]

Automatic Generation of Stream Descriptors for Streaming ArchitecturesLei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee. icpp 2010: 307-312 [doi]

2009

An intelligent IT infrastructure for the futurePrith Banerjee. hpca 2009: 3-4 [doi]

Sustainable data centers: enabled by supply and demand side managementPrith Banerjee, Chandrakant D. Patel, Cullen Bash, Parthasarathy Ranganathan. dac 2009: 884-887 [doi]

A software pipelining algorithm in high-level synthesis for FPGA architecturesLei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee. isqed 2009: 297-302 [doi]

2007

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA DesignsDavid Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee. isqed 2007: 595-601 [doi]

2006

Macro-models for high-level area and power estimation on FPGAsTianyi Jiang, Xiaoyong Tang, Prith Banerjee. ijspm, 2(1/2):12-19, 2006. [doi]

Dynamic Template Generation for Resource Sharing in Control and Data Flow GraphsDavid Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee. vlsid 2006: 465-468 [doi]

2005

Automatic extraction of function bodies from software binariesGaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee. aspdac 2005: 928-931 [doi]

An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA DesignSanghamitra Roy, Prith Banerjee. TC, 54(7):886-896, 2005. [doi]

Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly CodeDavid Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee. lcpc 2006: 76-90 [doi]

2003

An overview of a compiler for mapping MATLAB programs onto FPGAsPrith Banerjee. aspdac 2003: 477-482 [doi]

Adaptive computing: what can it do, where can it go?Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott. aspdac 2003: 463 [doi]

2001

Power Optimization of Delay Constrained CircuitsAnshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh. vlsi, 2001(2):125-138, 2001. [doi]

Parallelization of MATLAB Applications for a Multi-FPGA SystemAnshuman Nayak, Malay Haldar, Alok N. Choudhary, Prith Banerjee. fccm 2001: 1-9 [doi]

1988

Reconfiguration strategies in VLSI processor arraysKrishna P. Belkhale, Prith Banerjee. iccd 1988: 418-421 [doi]

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