Abstract is missing.
- An intelligent IT infrastructure for the futurePrith Banerjee. 3-4 [doi]
- Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systemsEiman Ebrahimi, Onur Mutlu, Yale N. Patt. 7-17 [doi]
- Voltage emergency prediction: Using signatures to reduce operating marginsVijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks. 18-29 [doi]
- A low-radix and low-diameter 3D interconnection network designYi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang. 30-42 [doi]
- Adaptive Spill-Receive for robust high-performance caching in CMPsMoinuddin K. Qureshi. 45-54 [doi]
- Design and implementation of software-managed caches for multicores with local memorySangmin Seo, Jaejin Lee, Zehra Sura. 55-66 [doi]
- In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnectsNiket Agarwal, Li-Shiuan Peh, Niraj K. Jha. 67-78 [doi]
- Practical off-chip meta-data for temporal memory streamingThomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos. 79-90 [doi]
- Soft error vulnerability aware process variation mitigationXin Fu, Tao Li, José A. B. Fortes. 93-104 [doi]
- Accurate microarchitecture-level fault modeling for studying hardware faultsMan-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve. 105-116 [doi]
- Eliminating microarchitectural dependency from Architectural VulnerabilityVilas Sridharan, David R. Kaeli. 117-128 [doi]
- Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metricsLide Duan, Bin Li, Lu Peng. 129-140 [doi]
- Opportunities beyond single-core microprocessorsMark D. Hill. 143-144 [doi]
- Multi-core demands multi-interfacesYale Patt. 147-148 [doi]
- Elastic-buffer flow control for on-chip networksGeorge Michelogiannakis, James D. Balfour, William J. Dally. 151-162 [doi]
- Express Cube Topologies for on-Chip InterconnectsBoris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu. 163-174 [doi]
- Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPsReetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. 175-186 [doi]
- Architectural ContestingHashem Hashemi Najaf-abadi, Eric Rotenberg. 189-200 [doi]
- Lightweight predication support for out of order processorsMark Stephenson, Lixin Zhang, Ram Rangan. 201-212 [doi]
- Blueshift: Designing processors for timing speculation from the ground upBrian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles. 213-224 [doi]
- PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor cachesMainak Chaudhuri. 227-238 [doi]
- A novel architecture of the 3D stacked MRAM L2 cache for CMPsGuangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. 239-249 [doi]
- Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large cachesManu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter. 250-261 [doi]
- Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchyNiti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell. 262-274 [doi]
- Reconciling specialization and flexibility through compound circuitsSami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam. 277-288 [doi]
- CAMP: A technique to estimate per-structure power at run-time using a few simple parametersMichael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi. 289-300 [doi]
- Variation-aware dynamic voltage/frequency scalingSebastian Herbert, Diana Marculescu. 301-312 [doi]
- Bridging the computation gap between programmable processors and hardwired acceleratorsKevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke. 313-322 [doi]
- Industrial perspectives panelParthasarathy Ranganathan. 325-326 [doi]
- A first-order fine-grained multithreaded throughput modelXi E. Chen, Tor M. Aamodt. 329-340 [doi]
- Characterization of Direct Cache Access on multi-core systems and 10GbEAmit Kumar, Ram Huggahalli, Srihari Makineni. 341-352 [doi]
- MRR: Enabling fully adaptive multicast routing for CMP interconnection networksPablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio. 355-366 [doi]
- Prediction router: Yet another low latency on-chip router architectureHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga. 367-378 [doi]
- Fast complete memory consistency verificationYunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan. 381-392 [doi]
- Hardware-software integrated approaches to defend against software cache-based side channel attacksJingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou. 393-404 [doi]
- Dacota: Post-silicon validation of the memory subsystem in multi-core designsAndrew DeOrio, Ilya Wagner, Valeria Bertacco. 405-416 [doi]
- Criticality-based optimizations for efficient load processingSamantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh. 419-430 [doi]
- iCFP: Tolerating all-level cache misses in in-order processorsAndrew D. Hilton, Santosh Nagarakatte, Amir Roth. 431-442 [doi]
- Feedback mechanisms for improving probabilistic memory prefetchingIbrahim Hur, Calvin Lin. 443-454 [doi]